AD1836A - Multichannel 96 kHz Codec AD1836A FEATURES 5 V...

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Multichannel 96 kHz Codec AD1836A FEATURES 5 V multichannel audio system Accepts 16-/18-/20-/24-bit data Supports 24-bit and 96 kHz sample rate Multibit Σ-∆ modulators with data directed scrambling Differential output for optimum performance ADCs: –92 dB THD + N, 105 dB SNR and dynamic range DACs: –95 dB THD + N, 108 dB SNR and dynamic range On-chip volume control with "auto-ramp" function Programmable gain amplifier for ADC input Hardware and software controllable clickless mute Digital de-emphasis processing Supports 256 × f S , 512 × f S , or 768 × f S master clock Power-down mode plus soft power-down mode Flexible serial data port with right justified, left justified, I 2 S compatible, and DSP serial port modes TDM interface mode supports 8 in/8 out using a single SHARC® SPORT 52-lead MQFP (PQFP) plastic package APPLICATIONS Home theater systems Automotive audio systems DVD recorders Set-top boxes Digital audio effects processors PRODUCT OVERVIEW The AD1836A is a high performance, single-chip codec that provides three stereo DACs and two stereo ADCs using ADI’s patented multibit Σ-∆ architecture. An SPI® port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1836A operates from a 5 V supply, with provision for a separate output supply to interface with low voltage external circuitry. The AD1836A is available in a 52-lead MQFP (PQFP) package. FUNCTIONAL BLOCK DIAGRAM DIGITAL FILTER Σ - DAC DAC1L DAC1R CLOCK MCLK COUT V REF CONTROL PORT CCLK CDATA CLATCH SERIAL DATA I/O PORT DIGITAL FILTER Σ - ADC1L 48kHz/96kHz PGA Σ - ADC2L 48kHz DIGITAL FILTER 48kHz DLRCLK DBCLK DSDATA1 DSDATA2 DSDATA3 ALRCLK ABCLK ASDATA1 ASDATA2 CAPL1 CAPL2 CAPR1 CAPR2 PD/RST AVDD AGND DVDD DGND 2 4 3 2 MUX PGA Σ - ADC2R 48kHz DIGITAL FILTER 48kHz DIGITAL FILTER Σ - DAC DAC2L DAC2R VOLUME DIGITAL FILTER Σ - DAC DAC3L DAC3R FILTR ADC1L ADC1R ADC2L1 ADC2L2 ADC2R1 ADC2R2 MUX VOLUME VOLUME VOLUME VOLUME VOLUME FILTD 48kHz/96kHz DIGITAL FILTER Σ - ADC1R 48kHz/96kHz 48kHz/96kHz Figure 1. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. Rev. 0
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AD1836A TABLE OF CONTENTS AD1836A—Specifications ............................................................... 3 Absolute Maximum Ratings ............................................................ 8 Pin Configuration And Pin Functional Descriptions .................. 9 Functional Overview ...................................................................... 11 ADCs ............................................................................................ 11 DACs ............................................................................................ 11 Clock Signals ............................................................................... 11 Reset and Power-Down ............................................................. 12 Serial Control Port ..................................................................... 12 Power Supply and Voltage Reference ....................................... 13 Serial Data Ports—Data Format ............................................... 13 SPI Control Registers ................................................................. 19 Outline Dimensions ....................................................................... 23 ESD Caution ................................................................................ 23 Ordering Guide .......................................................................... 23 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 24
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