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Unformatted text preview: BASIC COMPUTER ARCHITECTURE HOW COMPUTER SYSTEMS WORK A SIMPLE COMPUTER ARCHITECTURE PC REGISTERS +1 CONTROL UNIT MAIN MEMORY IR CONTROL SIGNALS MBR LATCH ALU CONTROL SIGNALS BUS 1 BUS 3 MAR BASIC COMPUTER ARCHITECTURE THE REGISTER ARRAY All modern CPU's have an array of registers usually at least 32 general purpose registers frequently some socalled gp registers have dedicated use usually contain one computer word can be accessed in one CPU cycle serve as source of operands serve as destination of results temporarily store intermediate results serve as index registers to access arrays Characteristics of registers Functions of registers Specialized registers floating point registers store constants ....frequently used values BASIC COMPUTER ARCHITECTURE THE REGISTER ARRAY Other specialized registers Consequences of the use of registers program counter stack pointer frame pointer base register instruction register memory address register memory buffer register some systems use "general purpose" registers to perform some of these functions faster program execution shorter instruction formats address mode flexibility BASIC COMPUTER ARCHITECTURE THE PROGRAM COUNTER The program counter.....PC stores address of next instruction to execute must be incremented after each instruction may be changed by function call or jump controls flow of program execution BASIC COMPUTER ARCHITECTURE THE INSTRUCTION REGISTER The instruction register contains the currently executing instruction holds instruction while it is being decoded opcode field provides input to control system indicating operation to perform contains addresses of operands to be used in operation contains destination address of result contains information about addressing modes to be used BASIC COMPUTER ARCHITECTURE THE ARITHMETIC/LOGIC UNIT The arithmetic/logic unit..... ALU performs arithmetic and logical functions add, subtract, multiply, divide, complement, shift...etc. function performed is determined by the control signals received will have input and output latches to hold operands and results BASIC COMPUTER ARCHITECTURE THE MEMORY ADDRESS REGISTER The memory address register MAR holds address of the location in memory to be accessed this may be the address of the next instruction to be fetched may be the address of an operand to be read from memory may be the address of information to be written to memory BASIC COMPUTER ARCHITECTURE THE MEMORY BUFFER REGISTER The memory buffer register MBR holds values to be transferred between main memory and the CPU data or instructions read from memory values to be written to memory most modern machines are capable of transferring more than a single word BASIC COMPUTER ARCHITECTURE THE CONTROL UNIT Control Unit provides control signals necessary to control the hardware of the CPU may be hardwired may be microprogrammed signals are generated by a combinational logic circuit faster less flexible harder to design and debug signals are stored in control memory slower than hardwired more flexible easier to design and debug control signals are needed to control functions of various hardware units and to direct the flow of information within the CPU BASIC COMPUTER ARCHITECTURE THE MEMORY UNIT Main Memory used to store programs and data volatile usually uses DRAM...dynamic random access memory most memory is byte addressable slower than static ram must be refreshed requires fewer transistors to implement improves packing density on IC...allowing larger, cheaper memories retrieve a single byte per memory access can be organized to access a full word or even multiple words per access cache memory is a distinct memory positioned between the CPU and MM faster smaller more expensive BASIC COMPUTER ARCHITECTURE THE BUS STRUCTURE CPU bus structure a bus is an "information path" connecting the various functional units within the CPU generally will be capable of transmitting one entire word in parallel the CPU will have multiple buses to improve the information transfer options within the CPU to maximize the flexibility and parallelism of the system will consist of one word length of "wires" or data paths ...
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