Appendix_C_Cache - Computer Architecture CSC 520 Appendix C...

Info icon This preview shows pages 1–11. Sign up to view the full content.

View Full Document Right Arrow Icon
Computer Architecture CSC 520 Appendix C Cache Memory
Image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Computer Architecture CSC 520 A typical memory heirarchy CPU Registers C A C H E Memory I/O Devices Size 500 bytes 64 Kbytes 512 Mbytes 100 Gbytes Speed 0.25 ns 1 ns 100 ns 5 ms Register Reference Cache Reference Memory Reference Disk Memory Reference
Image of page 2
Computer Architecture CSC 520 Cache Hit --- CPU finds requested data in Cache Cache Miss --CPU does not find requested data in Cache Cache is increasingly important because memory speed is not keeping up with CPU speed Cache runs at or near the speed of on-chip registers Cache heavily utilizes the principle of locality
Image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Computer Architecture CSC 520 We can pose 4 questions about any level of the heirarchy 1. Where can a block be placed in the upper level? 2. How is a block found if it is in the upper level? [block identification] 3. Which block should be replaced on a miss? [block replacement] 4. What happens on a write? [write strategy]
Image of page 4
Computer Architecture CSC 520 Cache --- generally the first level of memory heirarchy encountered once the address leaves the CPU The term “Cache” is now applied whenever buffering is employed to reuse commonly occurring items. Where can a block be placed in cache? There are three common basic organizations 1. Fully associative -- block can go anywhere 2. Direct mapped -- block I goes into I mod cache size 3. Set associative -- if we have four sets, block I goes into I mod 4 and then any block within the set. Majority of caches today are either direct mapped , two-way or four-way set associative.
Image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
CSC 520 COMPUTER ARCHITECTURE Main Memory block 0 1 2 3 4 5 6 7 Cache block 0 1 2 3 Direct Mapping
Image of page 6
CSC 520 COMPUTER ARCHITECTURE BLOCK 0 1 2 3 4 34 35 One memory block fits exactly into one cache frame frame set 0 0 1 2 1 3 4 2 5 6 3 7 A TWO-WAY SET ASSOCIATIVE MAPPING
Image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
CSC 520 COMPUTER ARCHITECTURE MATCH Address tag block frame 0 address tag block frame 1 address tag block frame N Real Address Block address word Main Memory Cache Fully Associative Mapping
Image of page 8
Computer Architecture CSC 520 How is a block found in cache Caches have an address tag on each block frame that gives the block address. The tag of every cache block that might contain the desired information is checked to see if it matches the block address of the CPU request. This is done in parallel, because speed is crucial. We use a valid bit to insure that the data is valid. The address is divided into a: tag field index offset We need only to check the tag field to see if block is in the block frame. The entire block would be present, so the offset must be there. The index was used to select the set being examined in the first place.
Image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Computer Architecture CSC 520 What happens on a write? Reads dominate cache accesses. All instruction accesses are reads and most instructions don’t write to memory.
Image of page 10
Image of page 11
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern