Appendix_C_Cache

Appendix_C_Cache - Computer Architecture CSC 520 Appendix C...

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Computer Architecture CSC 520 Appendix C Cache Memory
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Computer Architecture CSC 520 A typical memory heirarchy CPU Registers C A C H E Memory I/O Devices Size 500 bytes 64 Kbytes 512 Mbytes 100 Gbytes Speed 0.25 ns 1 ns 100 ns 5 ms Register Reference Cache Reference Memory Reference Disk Memory Reference
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Computer Architecture CSC 520 Cache Hit --- CPU finds requested data in Cache Cache Miss --CPU does not find requested data in Cache Cache is increasingly important because memory speed is not keeping up with CPU speed Cache runs at or near the speed of on-chip registers Cache heavily utilizes the principle of locality
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Computer Architecture CSC 520 We can pose 4 questions about any level of the heirarchy 1. Where can a block be placed in the upper level? 2. How is a block found if it is in the upper level? [block identification] 3. Which block should be replaced on a miss? [block replacement] 4. What happens on a write? [write strategy]
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Computer Architecture CSC 520 Cache --- generally the first level of memory heirarchy encountered once the address leaves the CPU The term “Cache” is now applied whenever buffering is employed to reuse commonly occurring items. Where can a block be placed in cache? There are three common basic organizations 1. Fully associative -- block can go anywhere 2. Direct mapped -- block I goes into I mod cache size 3. Set associative -- if we have four sets, block I goes into I mod 4 and then any block within the set. Majority of caches today are either direct mapped , two-way or four-way set associative.
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CSC 520 COMPUTER ARCHITECTURE Main Memory block 0 1 2 3 4 5 6 7 Cache block 0 1 2 3 Direct Mapping
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CSC 520 COMPUTER ARCHITECTURE BLOCK 0 1 2 3 4 34 35 One memory block fits exactly into one cache frame frame set 0 0 1 2 1 3 4 2 5 6 3 7 A TWO-WAY SET ASSOCIATIVE MAPPING
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CSC 520 COMPUTER ARCHITECTURE MATCH Address tag block frame 0 address tag block frame 1 address tag block frame N Real Address Block address word Main Memory Cache Fully Associative Mapping
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Computer Architecture CSC 520 How is a block found in cache Caches have an address tag on each block frame that gives the block address. The tag of every cache block that might contain the desired information is checked to see if it matches the block address of the CPU request. This is done in parallel, because speed is crucial. We use a valid bit to insure that the data is valid. The address is divided into a: tag field index offset We need only to check the tag field to see if block is in the block frame. The entire block would be present, so the offset must be there. The index was used to select the set being examined in the first place.
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Computer Architecture CSC 520 What happens on a write? Reads dominate cache accesses.
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This note was uploaded on 02/10/2012 for the course CSC 520 taught by Professor Simmons during the Fall '07 term at S. Alabama.

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Appendix_C_Cache - Computer Architecture CSC 520 Appendix C...

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