CSS 520 Project Fall 2007

CSS 520 Project Fall 2007 - CSS 520 Computer Architecture...

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CSS 520 Computer Architecture Design Project Fall Semester 2006 Due Monday, December 4, 2006 This is last day of class, 10% per DAY late penalty, not accepted after Dec 7. Working in teams of three, submit an architectural design for a processor with the following characteristics. Pipelined functional unit time requirements: Memory access/Instruction Fetch: cache access time (see below) Instruction decode process: 1 ns. Register access/ sign extend: 1 ns Max ALU function: 3 ns Simple add ALU: 1 ns Design your datapath for a pipelined machine. You decide how many stages. Provide a complete drawing of your datapath indicating all stages, functional units, multiplexors, registers, etc( you may indicate information passed between pipeline stages as a “black box” as done in the notes). Indicate all features that you include to improve the performance of your machine. Is your machine hardwired or microprogrammed? You must indicate how you deal with: Control hazards: Assume a branch instruction is encountered every 8 instructions on average and that 90% of the branches are taken. Deal with this as efficiently as possible with hardware and/or nops…no delayed branching. Data Hazards:
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This note was uploaded on 02/10/2012 for the course CSC 520 taught by Professor Simmons during the Fall '07 term at S. Alabama.

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CSS 520 Project Fall 2007 - CSS 520 Computer Architecture...

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