Pipelining_appendixA1

Pipelining_appendixA1 - COMPUTER ARCHITECTURE CSC 520...

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COMPUTER ARCHITECTURE CSC 520 PIPELINING Pipelining is an implementation technique whereby multiple instructions are overlapped in execution The Instruction cycle is broken into stages much like an assembly line. All modern computers use some form of pipelining, it is the key implementation technique used to make CPUs fast. Each stage is called a pipe stage or pipe segment They are connected to one another to form a pipe. Throughput of an instruction pipeline is determined by how often an instruction exits the pipe. Each of the stages must be ready to proceed at the same time.
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COMPUTER ARCHITECTURE CSC 520 Machine cycle -- time required to move an instruction through ONE stage of the pipeline. Goal is to balance the stages as closely as possible, so that each stage requires the same amount of time. If the stages are perfectly balanced, then the time per instruction on the pipelined machine is equal to: Time pipelined = Time unpipelined / number of stages Under such conditions, the ideal speedup due to pipelining would be equal to the numbers of stages [in the absence of other limiting factors] Such balance is rarely achieved and pipelining itself adds some overhead
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COMPUTER ARCHITECTURE CSC 520 Pipelining reduces the average execution time per instruction [also CPI]. The discussion in the text references the MIPS processor which has a RISC architecture. All operations on data apply to data in registers Only operations affecting memory are loads and stores Instruction formats are few and all are the same size. Three classes of instructions ALU instructions Load and Store instructions Branches and Jumps [control instructions].
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COMPUTER ARCHITECTURE CSC 520 A Simple Implementation of a RISC Instruction Set To evaluate the issues involved in pipelining, we first examine our RISC computer’s instruction interpretation cycle without pipelining. We assume every instruction requires, at most 5 clock cycles We focus only on a pipeline for an integer subset of a RISC architecture that consists of load-store word, branch , and integer ALU operations. The five clock cycles are: Instruction Fetch cycle IF Instruction Decode/Register Fetch cycle ID Execution/Effective Address cycle EX Memory Access cycle MEM Write-back cycle WB
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COMPUTER ARCHITECTURE CSC 520 Instruction Fetch Cycle (IF) IR mem[PC] PC PC + 4 Instruction Decode / Register Fetch cycle (ID) Decode the instruction and access the register file to read the operand values from the registers. A regs[IR 6…. .10 ] B regs{IR 11….15 ] Imm IR 16……31 Lower 16 bits stored for later use (actually sign extended to 32 bits)
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COMPUTER ARCHITECTURE CSC 520 Execution / effective address cycle (EX) The ALU operates on the operands prepared in the prior cycle. One of four functions depending on the MIPS instruction type. Memory reference
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This note was uploaded on 02/10/2012 for the course CSC 520 taught by Professor Simmons during the Fall '07 term at S. Alabama.

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Pipelining_appendixA1 - COMPUTER ARCHITECTURE CSC 520...

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