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Unformatted text preview: McGill University Faculty of Engineering Department of Electrical and Computer Engineering
EC SE—33OA — Introduction to Electronics Examiner. Dr. David V. Plant;
Associate Examiner. Dr. . me
Date: Thursday, December 7th, 2006
Time: 9:00 — 12. 00 Calculator: Faculty Standard Pertinent Information: 1) This is a closedbook examination, no notes permitted. There are 3 pages of equations
provided at the back of the examination. 2) The examination consists of 7 problems; you must answer all 7 problems.
3) The examination is worth 73 total points 4) The examination consists of 11 pages, including this page and the equations pages;
please ensure you have a COMPLETE examination paper. 5) Only the Faculty Standard Calculator is permitted. 6) Questions may be completed in any order, however ensure that you clearly identify
which part of which question you are attempting. Do NOT turn in this exam with your exam booklet Question #1 (10 points) a) [2 pts] A voltage ampliﬁer with an input resistance of 7.2kQ is connected to a voltage
source whose resistance is SkQ. Through measurements, it has been determined that
this ampliﬁer has a gain of 20.4 V/V when open—circuited at the output and 10.2 V/V
when a le resistance is connected at the load. Find the values of Ave, ROUT for this ampliﬁer. A transresistance ampliﬁer “AMPl” has RIN = 5009, ROUT = 7509, and RVO = 50 V/A.
A voltage ampliﬁer “AMP2” has Rm = 7.2kQ, Avo = 10V/V and ROUT = 5000. They are connected as shown in the ﬁgure below. Assume the constant voltage drop model for all diodes and Rs = 5k!) and RL = lkﬂ. +5V Transresistance Voltage Amp
Amp {AMPU (AMPZ) b) [2 pts] Redraw the circuit, replacing the ampliﬁers with their equivalent circuits.
(Leave the diodes and sources as they are). For parts c), d) and e), assume Vout = 0 and Vx = 0 when 15 = 0. c) [3 pts] Draw the currenttovoltage transfer characteristic (vout vs. is) of this circuit,
making sure to show the limits of the linear region. (Hint: it will help to ﬁrst sketch vX
vs. iS and compute Vout/VX) d) [1 pt] Based on your transfer characteristic, what input current‘results in the
maximum symmetric voltage swing at Vent? e) [2 pts] By adding EXACTLY THREE diodes, show how you could modify the
circuit so that the output saturates at Voutmax = 6.4 V and Vout_min = 3.7 V. (Hint: You
may also use the voltage source +5V and 3V) Question #2 (12 pts) Consider the circuit below. All diodes are identical and all capacitors and inductors are
inﬁnite (an inﬁnite inductor is a shortcircuit at DC, and an opencircuit for signals). Use
the constant voltage drop model. D4 inﬁnite R2=175S2;R3=18009;R4=7209 a) [3 pts] Assume that R1 = 1009 and determine the DC current in each diode.
Clearly state and justify your assumptions. b) [2 pts] What is the smallest value resistor R2 can have so that D4 is conducting? c) [2 pts] If resistor R1 is set to zero (shortcircuited), determine the DC current
ﬂowing in D1. For parts d)e), assume R1 = 1009 as in part a). d) [2 pts] Draw the smallsignal model of this circuit. Do not calculate any small
signal values. e) [2 pts] Find an expression for the voltage gain vow/vS in terms of resistances. f) [1 pt] The smallsignal model for a diode is a resistor. Brieﬂy (in one or two
lines) explain why this model is only accurate for “smallsignals”. Question #3 (12 points) Consider the following circuit. Assume all BJTs are in the active mode and have 3=99. R1 = 100k!) R4 = 2k!) I = 2mA R2 = 45k!) R5 = 20k!) VDD = 5V
R3 = 5k!) R6 = 1k!) For questions a) and b), you may use VBE = 0.7V.
a) [1 pt] What value of V3 puts Q3 on the active/saturation boundary? b) [2 pts] Assuming VB = 3V, ﬁnd the current ﬂowing in each diode and the
collector current of each BJ T. For questions c) to e), you must decide whether to include or neglect the Early effect in your analysis for each transistor. Give your answers in terms of [3, resistances, and
smallsignal parameters. Do not calculate numerical values for these questions. c) [3 pts] Draw the smallsignal equivalent circuit, assuming the current source
has output resistance to]. d) [4 pts] Find expressions for vl/vin, vz/vl, vol/v; and vo/vol. e) [2 pts] Find expressions for RIN and ROUT. Question #4 (9 points) The circuit below is composed of a FET differentialpair (M1, M2), two common—
collector output voltage buffers (Q1, Q2), and a biasing current mirror arrangement (Q3
through Q7). All of the BJTs in the cirCuit are identical, and so are the two F ETs M1 and
M2. You may assume VBE=0.7V and B=100 for all BJTs. +VDU +Vou
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+VnD 1:.) r" 1.... “\/‘..’\.—— l 5'33) ' #15 V°2
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V }RREF Rm V V g Raw
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l J 5 v I
(WM: /’ / _ ‘, VDD V
1" a“: Hm ““1. “‘1:
l 03 0t 05 I as
d7 .an *7 Vw “7.7 a) [2 pts] If IVDD = 5V, ﬁnd the value of RREF such that IM = 1mA. b) [1 pt] What is the differential smallsignal input resistance, RIN, of the FET
differential pair? For the remainder of this problem, you may neglect CLM and the Body Effect for
the FETs. You must decide whether to include the Early Effect for each BJT. Also,
assume each transistor in the current mirror (Q36) has a output resistance roM.
Please give answers in terms of the smallsignal parameters of the FETs and BJTs. c) [2 pts] Find an expression for the differential output resistance of this ampliﬁer
Rout and the single—ended input resistance RA. d) [4 pts] Find expressions for the differential voltage gains V01 /VS = (VD1 — VD2)/K
and V02 /Vs =(V51_ V52)/Vs I Question 5 (10 points) Consider the following twostage FET ampliﬁer circuit. Assume that all the FETs are in
the saturation mode. You must decide whether to include or neglect Channel Length
Modulation according to the rules established in class. Also, you must include the Body Effect where appropriate (you may also use gmb = xgm to simplify expressions). Give your answers in terms of resistances shown and small—signal parameters. Stage 1 Stage 2 a) [1 pt] Identify the type of ampliﬁers represented by M1 and by M2 (for
example, are they CGA, CSA or CDA?) b) [3 pts] Draw the smallsignal equivalent circuit model.
c) [1 pt] Find an expression for Rm. (1) [2 pts] Find an expression for vx/vs, e) [2 pts] Find an expression for vo/vx, f) [1 pt] Find an expression for the total voltage gain vo/vs. Question 6 (12 points) Consider the following twostage BiCMOS ampliﬁer circuit composed of MA and Q3.
The rest of the circuit features a BiCMOS current source, consisting of (1) a push
conﬁguration of BJTs (Q1 and Q2) to generate Inf (this is called a “Widlar” current
source), and (2) a pull conﬁguration current mirror of MOSFETs (M1, M2, and M3). Given: VCC = 5V, [3 = 99, R1 = IOkQ, R2 = 30kg, Vt = 1V and (WI/L1) = 2><(W2/L2). Q1 is active mode, and Q2 is exactly on the edge of saturation and active modes. V Vcc CC CC a) [3 pts] Calculate the reference current Iref (Hint: Focus 0n_the BJTs, apply KCL and
[VBEI = 0.7 V). b) [1 pt] What is the current IX in terms of Iref? c) [1 pt] What is the minimum voltage VX required to keep M2 in the saturation mode?
(Hint: recall that Q2 is on the edge of saturation and active modes). For (1) — 1) Assume that MA is in saturation mode and that QB is active mode.
Include Channel Length Modulation and the Early Effect, neglect the Body Effect. d) [3 pts] Draw the smallsignal equivalent circuit. (Hint: draw only what is in the signal
path: MA, Q3, and “part” of M3. .. the other transistors are not required!) e) [2 pts] Find expressions for RDM and Ram (you may use RDM in your answer for Raw). f) [2 pts] Find expressions for vy/vm and vo/vy (in terms of RDM and Rug as needed). Question 7 (8 points) Consider the inverter circuit and voltage transfer characteristic. Assume Vm = th = IV. I 'II ' III 'IV' V
W vO I I I :
I I I I
I I I I
I I I I
5V I I I
I I I I
I I I I
I I I I
i I 
M1 I I I
I I I
I I I
I I I
I I I
I I I
I I I
V0 I I I
I I I
I I I
I I I
I I I
M2 5 I I
I I I
 I l
I I I
I I
I I
I I
I I 5V 3) [1 pt] If kn’ = 2.5 kp’ and (W/L)n= 4, what ratio ’(W/L)p would ensure that the
voltage transfer characteristic is symmetric? b) [2 pts] For every section of the VTC (I through V), state the mode of
operation of M1 and M2. c) [1 pt] What are the values of VOL and VOH? d) [2 pts] In what region(s) of the VTC are VIL and VIH located? What is the
slope of the VTC at VIL and VIH? e) [2 pts] Draw the CMOS circuit implementing a NOR gate, i.e. implementing
the Boolean function V0 = VA + VB . FORMULA SHEETS Diodes:
i = [S exp(v/nVT —1) rd 2 I’ZVt/ID BJTs: iC :1 S eXPQBE/ VT) l
132%
iE =l—C
a
z (1—a)i —i—E
B E ﬂ+l
iE :(ﬂ+1)i3
g —i In —E —a
m VT 6 IE IC gm
gig ﬁzz
13 gm 1C
I;r =(ﬂ+1)re
ﬂ 1 a:_ﬂ_ ﬂ+1 FETs: NMOS:
Cutoff: VGS < Vt [D = 0
. . l W 1 2
Trlode. VGS > V, [D = kn —L—[(Vcs — V1)VDS _ TVDS ]
VDS < VGS ‘ Vt
V > V
Saturation: GS t W 2
I =Lk'—V —V 1+,1V
VDS>VGS—Vt D 2 nL(GS t)( DS) Body effect: Vt = VtO + 7( 12¢f + V33 _ X2¢f) PMOS:
Cutoff:
I = 0 VGS > Vt D Triode: Vos < V} ID = k; gkr/GS —V,)VDS 4%Vgs]
VDS > VGS _ Vt V < V Saturation: GS t I D = §kl’, % (VGS — Vr )2 (1 + AVDS)
VDS < VGS _ Vt Body effect: W = Ko + 74% _ M) 10 SMALL SIGNAL , W
gm anYO/Gs _VIX1+/I'VDS) W
gm =WEV1+A'VDS\/Z 11 ...
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