ECSE_330_december2007

ECSE_330_december2007 - ECSE 330 Final Exam McGill...

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Unformatted text preview: ECSE 330 Final Exam McGill University Faculty of Engineering Department of Electrical and Computer Engineering ECSE—330A — Introduction to Electronics Date: Thursday, December 6th, 2007 v A— Time: 9:00— 12:00 ‘1 Calculator: Faculty Standard Pertinent Information: 1) This is a closed-book examination, no notes permitted. There are 3 pages of equations provided at the back of the examination. 2) The examination consists of 7 problems; you must answer all 7 problems. 3) The examination is worth 73 total points 4) The examination consists of 11 pages, including this page and the equations pages; please ensure you have a COMPLETE examination paper. 5) Only the Faculty Standard Calculator is permitted. 6) Questions may be completed in any order, however ensure that you clearly identify which part of which question you are attempting. Do NOT turn in this exam with your exam booklet ECSE 330 Final Exam Question #1 (10 points) Consider the multi-stage cascade of op-amps shown below. Assume that all op—amps are ideal. StageA 5 i Stage C Rim . R1 «fit RD; I V03 v2 c_2 J \,_i ? é _ Rm . R2 RT‘I a) [1 pt] Find an expression for V01 in terms of V1 and V2 b) [1 pt] Find an expression for V02 in terms of V01 c) [1 pt] Find an expression for V03 in terms of V1 and V2 d) [5 pts] Find expressions for the following: 1- Rinl II. Ring III. Ring IV. Rin3 V. Rout e) [2 pts] If the op-amp in Stage B is otherwise ideal but now has a finite open-loop voltage gain ‘A’ such that V02 = A-(V+-V_), show that: 53 E: 1+er V01 1+h 1+ AR” ECSE 330 Final Exam Question #2 (12 points) In the circuit below, assume that all diodes are ON and that they are identical. I Rin a) [3 pts] Using the exponential model of the diode, find an expression for the DC voltage V0, in terms of Vcc, and the diode parameters n and Vt For parts (b) to ((1), let rdl-rds represent the small—signal resistances of Dl-DS, respectively. b) [3 pts] Draw the small-signal equivalent circuit. c) [1 pt] Find an expression for the small-signal voltage gain, vo/vs. d) [1 pt] Find an expression for the input resistance, Rm. e) [4 pts] For the following circuits, sketch vs. time roughly what the transient output Vout will look like assuming a sinusoidal input Vin with an amplitude of 2V (i.e. 4Vpk_pk). i) D1 11) R1 ' _ A. 0—.—. ECSE 330 Final Exam Question #3 (7 points) Consider the following circuit. Assume all BJTs have [VBEI = 0.7V. Neglect the Early effect. Given VDD = 4.2 V, ,6 = 99, Rref= IkQ, and R5 = 1009. a) [1 pt] Determine the current I. b) [2 pts] Determine the value for the resistor RA. c) [2 pts] Assuming I = 3.5 mA and RA = IOOkQ, determine the value for R3 that puts Q2 and Q3 on the edge of saturation-active mode. d) [2 pts] Assume R5 = 0, and that Q2 and Q3 are exactly at the edge of saturation-active boundary. Determine the Voltage V0. (Hint: you do not need to know I or RA). ECSE 330 Final Exam Question #4 (12 points) Consider the following three—stage BiCMOS amplifier circuit composed of Q1, M1 and M2. For Q1, fl = 99, VT = 25 mV, and you can neglect the Early effect (i.e. VA = 00). M1 and M2 are identical and you may neglect the body effect but you must include the channel length modulation for both M1 and M2. You may assume that Q1 is active, and M1 and M2 are in saturation. a) [1 pt] Given RF = IOOkQ, calculate the value of the emitter current IE. b) [2 pts] Calculate the value of RE required to have a collector voltage Vc1 = 2.5 V. c) [3 pts] Draw neatly a small-signal model for this circuit. d) [2 pts] Find an expression for the small—signal voltage gain vx/vm. You may refer to Rinl if you find it helpful. Do not simplify your final expression. (Hint: You will need to make use of KCL — this cannot be done by inspection). e) [1 pt] Find an expression for vy/vx. f) [1 pt] Find an expression for vow/vy. g) [1 pt] Find an expression for Rmz. h) [1 pt] Find an expression for Raw. UI ECSE 330 Final Exam Question #5 (12 points) Consider the circuit shown below, Which consists of a current mirror (Ql-Q4), a diff-pair (Q5 & Q6) with an active load (Q7 & Q8), and an output emitter-follower (Q9 & Q10). You are also told that Vcc = 5V and RE = 1.6kQ. :55. Vac 'A .43.. Vac 3:; HI. 3/ I Q? 3—; QB " “‘1 i . vm ’3— foe V3, .——-— —— - 1 l/" LN. I -' L. Q5 05 / —{‘ _ _« 3/ VCC —- VCM+VJ2 ‘ ‘ ch-Vof2 “mom REE-J. :EERE ‘—-[—hr “Du” :: E' ‘7 ' g, Rae: I _ _: VIM — 3 io lo llfl ' i r I 3.: I f I/ 01 J: r — --- - a 04 | .ri. Assume all BJT’s are active-mode with |VBE| = 0.7, VA = 25V All BJTs have [3 = 100 except Q7 & Q8 -— assume Q7 & Q8 have no base current (B = 00). a) [2 pts] Choose the value of RREF that will create a bias current I0 = 2mA (neglect the Early effect in this part, and write your final answer with a precision of 0.000). b) [2 pts] Find the minimum M maximum values of VCM that will keep the diff-pair and Q2 in the active mode (assume VBc = 0 is the active/sat boundary)? c) [4 pts] Draw the small-signal model for the appropriate “half—circuit” (I suggest T- models). Make simplifying substitutions for BJTs that are not in the signal path. Include the Early effect where it is appropriate according to the rules discussed in class. Also, calculate the values of the relevant small-signal parameters for each BJT. vout+—Vout— Va in terms of the small-signal parameters and resistors of the circuit. Do NOT calculate it. d) [3 pts] By inspecting your model, find an expression for the differential gain e) [1 pt] What is the purpose of an active load like Q7-Q8? Why not just use a resistor? ECSE 330 Final Exam Question 6 (11 points) Consider the circuit shown below. You may assume all capacitors are infinite, and all FETs are identical and are in the active mode. You must decide whether or not to include Channel Length Modulation based on the rules discussed in class. Include the Body Effect where appropriate. Vcc ' Vcc '4}- VCC 2‘ R0312 gm e -:—l ]|__M1 _ T _ -) M4 R7 out I lRiM < R4 ! _" . — I 4L gT‘ ‘ i l a) [4 pts] Carefully and neatly draw a small-signal model for this circuit. In terms of the resistances shown and the small-signal parameters of the FETs, use your model to find an expression for the following: b) [1 Ptl Rinl c) [1 Pt] Routz d) [2 pts] Rout Vour e) [3 pts] The overall voltage gain in ECSE 330 Final Exam Question #7 (9 points) The following circuit imSlements an inverter logic function using matched NMOS and PMOS FET transistors: k"'(WL n = kp'(%)p 5 V "in ti 4| "0 For part (a) you can neglect channel length modulation. , L a) [2 pts] Sketch the voltage transfer characteristic (VTC) V0 vs. VIN for DC inputs ranging from 0 to 5V. Label VIL, VIH, VOL, and VOH on your sketch. For part (b) to (d), you must include channel length modulation. b) [2 pts] Draw the small-signal equivalent circuit. c) [2 pts] Show that: v in d) [1 pt] Find an expression for the small-signal output resistance, Rout. e) [2 pts] The following circuit has a single NPN and PNP BJT with B = 100. {A +5j _5 Q1 \L a | g. V. v . v Vin 10 K0 Vout . I/i 1 K0; 5 02 For an input voltage Vin = +5 V, what mode of operation is each transistor in? Show how you came to your result. (HINT: One transistor will be in cutoff) n J ECSE 330 Final Exam FORMULA SHEETS Diodes: i=IS exp(v/nVT —1) rd 2 n BJTs: iC =15 CXPQBE/ i 13 =—2 1E =l—C a z —(1—a)i ——iE— B E ,B+1 iE =w+DlB gm :I_C 7; 2E zaE V} IE ’2: :E Zfi ’13 =E 18 gm IC I;r =(,B+1)re flzi 052$ 3+1 ECSE 330 Final Exam FETs: NMOS: Cutoff: VGS < Vt Triode: VGS > V, V DS < VGS — V V > V Saturation: GS t VDS > VGS _ V1 Bodyeffect V, = V“) + A 2% + V53 — x/Mf) PMOS: Cutoff: VGS > V; Triode: VGS < Vt VDS > VGS _ Vt VGS < Vt S aturati on : VDS < VGS " V: Body effect: I 10:0 , W ID kn _L—[(VGS _ V1)VDS _ ;_VD2S] ID ,W é—kn TO/GS _V1)2(1+ lVDS) 1D=0 , W ID=kpf[(VG "V:)VD ‘17V02s] VGS "'Vr)2(1+’1VDs) w=mow+y< mam—M) 10 ECSE 330 Final Exam F ETS SMALL SIGNAL ,W gm =knT(VGS _Vr)(1+/1'VDS) W gm =\/§kir;\/;V1+A'VDS\/Z 11 ...
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ECSE_330_december2007 - ECSE 330 Final Exam McGill...

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