Ch9-UART

Ch9-UART - Universal Asynchronous Receiver Transmitter Dr....

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Unformatted text preview: Universal Asynchronous Receiver Transmitter Dr. V. Kpuska 2/11/12 Veton Kpuska 2 BF533 UART Port Controller u Reference: ADSP-BF533 Blackfin Processor Hardware Reference (doc: BF533- 5689413713358021532_hwr.pdf) 2/11/12 Veton Kpuska 3 BF533 UART Port Controller u The Universal Asynchronous Receiver/Transmitter (UART) is a n full-duplex peripheral compatible with PC-style industry-standard UARTs. n The UART converts data between serial and parallel formats. u The serial communication follows an asynchronous protocol that supports various n word lengths, n stop bits, and n parity generation options. u The UART includes interrupt handling hardware. Interrupts can be generated from 12 different events. 2/11/12 Veton Kpuska 4 BF533 UART Port Controller u The UART is a DMA-capable peripheral with support for separate TX and RX DMA master channels. u It can be used in either n DMA or n programmed non-DMA mode of operation. The non-DMA mode requires software management of the data flow using either interrupts or polling. u The DMA method requires minimal software intervention as the DMA engine itself moves the data. See Chapter 9 of HRM, Direct Memory Access for more information on DMA. u Either one of the peripheral timers can be used to provide a hardware assisted autobaud detection mechanism for use with the UART. See Chapter 15 of HRM, Timers, for more information. 2/11/12 Veton Kpuska 5 Serial Communication u The UART follows an asynchronous serial communication protocol with these options: n 5 8 data bits n 1, 1, or 2 stop bits n None, even, or odd parity n Baud rate = SCLK/(16 Divisor), where SCLK is the system clock n frequency and Divisor can be a value ranging from 1 to 65536 u All data words require a start bit and at least one stop bit. With the optional parity bit, this creates a 7- to 12-bit range for each word. u The format of received and transmitted character frames is controlled by the Line Control register ( UART_LCR ). Data is always transmitted and received least significant bit (LSB) first. 2/11/12 Veton Kpuska 6 Bitstream on the TX Pin Start Bit LSB B0 B1 B2 B3 B4 B5 B6 B7 Parity Bit Optional ODD or EVEN Data Bits Stop Bit 2/11/12 Veton Kpuska 7 UART Control and Status Registers u The processor provides a set of PC-style industry-standard control and status registers for each UART. u Control and Status Registers are Memory Mapped Registers (MMR)....
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Ch9-UART - Universal Asynchronous Receiver Transmitter Dr....

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