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ISSI_SDRAM_42S83200B-16160B

ISSI_SDRAM_42S83200B-16160B - IS42S83200B IS42S16160B 32Meg...

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IS42S83200B IS42S16160B Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. C 03/13/07 Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. FEATURES Clock frequency: 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Power supply V DD V DDQ IS42S83200B 3.3V 3.3V IS42S16160B 3.3V 3.3V LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh 8K refresh cycles every 64 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Available in Industrial Temperature Available in 54-pin TSOP-II and 54-ball BGA (x16 only) Available in Lead-free OVERVIEW ISSI 's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM MARCH 2007 KEY TIMING PARAMETERS Parameter -6 -7 Unit Clk Cycle Time CAS Latency = 3 6 7 ns CAS Latency = 2 8 10 ns Clk Frequency CAS Latency = 3 166 143 Mhz CAS Latency = 2 125 100 Mhz Access Time from Clock CAS Latency = 3 5.4 5.4 ns CAS Latency = 2 6.5 6.5 ns IS42S83200B IS42S16160B 8M x 8 x 4 Banks 4M x16x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball BGA
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2 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 03/13/07 IS42S83200B, IS42S16160B DEVICE OVERVIEW The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V DD and 3.3V V DDQ memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is orga- nized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.
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