Ch5-Processor_Design-Advanced_Topics

Ch5-Processor_Design-Advanced_Topics - Computer...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Computer Architecture Processor Design-Advanced Topics February 11, 2012 Veton Kpuska 2 Chapter Outline 5.1 Pipelining A pipelined design of SRC Pipeline hazards 5.2 Instruction-Level Parallelism Superscalar processors Very Long Instruction Word (VLIW) machines 5.3 Microprogramming Control store and micro-branching Horizontal and vertical microprogramming February 11, 2012 Veton Kpuska 3 The Pipeline and the Assembly Line Executing Machine Instructions versus Manufacturing Small Parts Part manufacture Make end plate Memory access ALU operation Fetch operands Fetch instruction Instruction interpretation and execution Register write (a) Without pipelining/assembly line (b) With pipelining/assembly line Polish part Cut part Drill part Select part Part manufacture Package part Polish part Cut part Drill part Select part Package part Bottom plate Top plate End plate Cover plate Center plate sub r2, r5, 1 add r4, r3, r2 st r4, addr1 Id r2, addr2 shr r3, r3, 2 Fetch Instruction Instruction Interpretation and Execution Fetch Operands add r4, r3, r2 ALU Operation Memory Access Register Write February 11, 2012 Veton Kpuska 4 The Pipeline Stages 5 pipeline stages are shown 1. Fetch instruction 2. Fetch operands 3. ALU operation 4. Memory access 5. Register write Example of 5 instructions executing at different stages in pipeline: shr r3, r3, #2 ;Storing result into r3 sub r2, r5, #1 ;Idleno memory access needed add r4, r3, r2 ;Performing addition in ALU st r4, addr1 ;Accessing r4 and addr1 ld r2, addr2 ;Fetching instruction February 11, 2012 Veton Kpuska 5 Pipelining Instruction Processing Pipeline stages are shown top to bottom in order traversed by one instruction Instructions listed in order they are fetched Order of instructions in pipeline is reverse of listed If each stage takes 1 clock: every instruction takes 5 clocks to complete some instruction completes every clock tick Two performance issues: instruction latency and instruction bandwidth February 11, 2012 Veton Kpuska 6 Dependence Among Instructions Execution of some instructions can depend on the completion of others in the pipeline Pipeline Stalls : One solution is to stall the pipeline early stages stop while later ones complete processing Data Forwarding : Dependences involving registers can be detected and data forwarded to instruction needing it, without waiting for register write Dependence involving memory is harder and is sometimes addressed by restricting the way the instruction set is used: Delayed Load : Decree Values loaded from memory into the register file cannot be accessed until tow instructions later. instructions later....
View Full Document

Page1 / 85

Ch5-Processor_Design-Advanced_Topics - Computer...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online