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Ch7-MemorySystemDesign

Ch7-MemorySystemDesign - Computer Architecture Memory...

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Computer Architecture Memory System Design
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February 11, 2012 Veton Këpuska 2 Chapter Outline 7.1   Introduction: The Components of the Memory System 7.2   RAM Structure: The Logic Designer’s Perspective 7.3   Memory Boards and Modules 7.4   Two-Level Memory Hierarchy 7.5   The Cache 7.6   Virtual Memory 7.7   The Memory Subsystem in the Computer
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February 11, 2012 Veton Këpuska 3 Introduction So far, we’ve treated memory as an array of words limited  in size only by the number of address bits.  Real world issues arise: cost speed size power consumption volatility ...
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February 11, 2012 Veton Këpuska 4 Topics Covered Memory components: RAM memory cells and cell arrays Static RAM—more expensive, but less complex Tree and matrix decoders—needed for large RAM chips Dynamic RAM—less expensive, but needs “refreshing” Chip organization Timing ROM—Read-only memory Memory boards Arrays of chips give more addresses and/or wider words 2-D and 3-D chip arrays  Memory modules Large systems can benefit by partitioning memory for separate access by system components fast access to multiple words
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February 11, 2012 Veton Këpuska 5 Topics Covered The memory hierarchy : from fast and expensive to slow and  cheap Example: Registers  Cache  Main Memory  Disk At first, consider just two adjacent levels in the hierarchy The cache: High speed and expensive Kinds: Direct mapped, associative, set associative Virtual memory—makes the hierarchy transparent Translate the address from CPU’s logical address to the  physical address where the information is actually stored Memory management—how to move information back and  forth Multiprogramming—what to do while we wait The Translation Look-aside Buffer - “TLB” helps in  speeding the address translation process Overall consideration of the  memory as a subsystem
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February 11, 2012 Veton Këpuska 6 The CPU–Memory Interface Sequence of events: Read: 1. CPU loads MAR, issues Read, and REQUEST 2. Main memory transmits words to MDR 3. Main memory asserts COMPLETE Write: 1. CPU loads MAR and MDR, asserts Write, and REQUEST 2. Value in MDR is written into address in MAR 3. Main memory asserts COMPLETE CPU m Main memory Address bus Data bus s Address 0 1 2 3 2 m – 1 A 0 – A m– 1 D 0 – D b– 1 R/W REQUEST COMPLETE MDR Register file Control signals m w w MAR b
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February 11, 2012 Veton Këpuska 7 The CPU–Memory Interface (cont’d.) Additional points: If b < w, main memory must make (w/b) b-bit transfers Some CPUs allow reading and writing of word sizes < w Example: Intel 8088: m = 20, w = 16, s = b = 8
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