ECE4551-MidTerm-ExamII-Solutions

ECE4551-MidTerm-ExamII-Solutions - ECE 4551 Fall 2003...

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ECE 4551 – Fall 2003 Computer Architecture MIDTERM EXAM II Tuesday, November 11 th 2003 Duration: 75 minutes LAST NAME (please, PRINT your last name) FIRST NAME (please, PRINT your first name) Instructions This exam consists of 5 questions (60 points total) and 1 problem (10+20+20=50 total points), which gives a total of 110 points out of 100; 10 points are extra credit. For the questions provide a brief but complete answer. Read each question or problem statement carefully. Please, circle or box-in your final answers to the problems , if applicable. Solutions to this exam will be posted during the upcoming weekend on the class’ website. If you have any questions, please let me know. Final note; Keep the handouts on your desk. Thank you & Good Luck! Dr. Veton Këpuska ECE 4551 - Midterm Exam II Page 1 of 11
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Questions with Short Answers (60 points total; questions are not equally weighted) Question 1 (10 points) What is the reason that drove computer architects towards pipelined architectures? Answer: To improve execution speed/throughput of the CPU. Question 2 (10 points) Compute estimated speedup of the pipelined SRC compared to 1-bus SRC architecture. Assume that on average there are 2 pipeline stalls for every 7 instructions. Also assume that all SRC instructions take 5 clock cycles. Clock period and instruction count are the same for both architectures. Answer: 5 2857 . 1 7 9 : % 89 . 288 2857 . 1 2857 . 1 5 % = = = = - = - = o w w w w o w CPI CPI where CPI CPI CPI Speedup ECE 4551 - Midterm Exam II Page 2 of 11
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Question 3 (20 points) Pipelined SRC architecture: a) In order to design a pipelined version of the SRC architecture, what changes must be made to the original architecture (i.e., 1-bus SRC architecture)? b) What are the issues involved when deciding about the structure of the pipeline itself and what does the design process entail? Answer: a) i. Special incrementer for PC is necessary. ii. Separation of Data Memory from Program Memory. iii. ALU operation to be completed in 1 cycle. iv. 3-port register file (simultaneous access of three registers for 2 reads and one write) v. Pipeline registers (e.g., IR2, PC2) vi. Pipeline Mutliplexers b) i. Group instructions based on similarity of execution (e.g., ALU instructions) ii. Identify stages of execution of each instruction group iii. Design the pipeline so that each stage of instruction will execute in 1 cycle ECE 4551 - Midterm Exam II Page 3 of 11
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Question 4 (10 points) What are two basic approaches to avoid hazards that must be used in pipeline architecture
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This note was uploaded on 02/10/2012 for the course ECE 4551 taught by Professor Johnhadjilogiou during the Fall '09 term at FIT.

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ECE4551-MidTerm-ExamII-Solutions - ECE 4551 Fall 2003...

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