Processor_Design2

Processor_Design2 - Computer Architecture Processor Design...

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Unformatted text preview: Computer Architecture Processor Design February 11, 2012 Veton Kpuska 2 Chapter Outline The Design Process A 1-Bus Microarchitecture for the SRC Data Path Implementation Logic Design for the 1-Bus SRC The Control Unit The 2- and 3-Bus Processor Designs The Machine Reset Machine Exceptions February 11, 2012 Veton Kpuska 3 The Design Process Focus from RTN machine description to computer system design: Design of the central processing unit Logic designers point of view RTN and logic design tools presented in Chapter 2 will be used extensively. Goal is not simply to present a design of SRC but also to do the design in the way a designer would approach it. February 11, 2012 Veton Kpuska 4 The Design Process In Chapter 2, the informal description of SRC was formalized by means of an RTN description. Some of the machine hardware was also specified: Programmer-visible registers. Next steps: 1. Specification of the data path. The set of interconnections and auxiliary registers needed to accomplish the overall changes an instruction makes in the programmer-visible objects. RTN useful in describing the actions that take place in the data path. Assumptions about how hardware components behave in describing the data path. This set of assumptions becomes a specification for the logic design of the data path hardware. 1. Hardware design based on specifications. Control signals must be contemplated that must be generated to cause actions to take place. Strobes to load registers Gates to apply outputs to a bus. 1. Control Unit design Generates the control signals in correct order to effect the correct data path activity. February 11, 2012 Veton Kpuska 5 Abstract and Concrete Register Transfer Descriptions The abstract RTN for SRC in Chapter 2 defines what, not how A concrete RTN uses a specific set of real registers and buses to accomplish the effect of an abstract RTN statement Same abstract RTNs that implement the same ISA could have different concrete RTNs. February 11, 2012 Veton Kpuska 6 Fig 4.1 Block Diagram of 1-Bus SRC ALU C C A 31. .0 32 31 A D P C i n G r a W t R0 R31 31 IR MA To memory subsystem Data Path Main memory Memory bus Figures 4.2, 4.3 Control Unit CPU Control unit inputs Control signals out MD PC A B 32 32-bit general purpose registers Figure 4.11 Input/ output February 11, 2012 Veton Kpuska 7 Fig 4.2 High-Level View of the 1-Bus SRC Design ALU C C A 31. .0 32 31 R0 R31 31 IR MA To memory subsystem MD PC A B 32 32-bit general purpose registers February 11, 2012 Veton Kpuska 8 Constraints Imposed by the Microarchitecture...
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This note was uploaded on 02/10/2012 for the course ECE 4551 taught by Professor Johnhadjilogiou during the Fall '09 term at FIT.

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Processor_Design2 - Computer Architecture Processor Design...

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