Lab08 - (2) Draw “2-Bit Adder” digital logic circuit in...

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1 ECE1551 – Digital Logic Lab (2-Bit Adder) 1-Bit Adder (Half-Adder) 1. Before designing 2-Bit Adder, understand below 1-Bit (or Half) Adder 2. 1-Bit Adder Logic Circuit is usually given below circuit. 3. Understand the truth tables of X-OR gate and 1-Bit (or Half)-Adder X-OR gate Truth Table A B Output 0 0 0 0 1 1 1 0 1 1 1 0 1-Bit Adder Truth Table Input Output A 0 B 0 S 0 C 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 A 0 B 0 S 0 C 0 X-OR
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2 2-Bit Adder Specification: Input argument: A(A 0 ,A 1 ), B(B 0 , B 1 ) Output argument: S(S 0 ,S 1 ) Carrier output: C(C 0 , C 1 ) (1) Create New Project for Argument Lab in Xilinx ISE 8.1i.
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Unformatted text preview: (2) Draw “2-Bit Adder” digital logic circuit in Schematic. (3) Initialize timing for input bits in Test Bench Waveform 3 • Below screen is one example of initial timing 4 (4) Run the designed circuit through ModelSim Simulator • Compare simulation result with your lecture notes • Below screen is the simulation result with previous initial timing (5) Save your circuit design, initial timing, and modelsim result as image files and link to your webpage...
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This note was uploaded on 02/11/2012 for the course ECE 1551 taught by Professor Hadjilogiou during the Fall '11 term at FIT.

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Lab08 - (2) Draw “2-Bit Adder” digital logic circuit in...

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