2011Fall_EEE335_Lab3

# 2011Fall_EEE335_Lab3 - Lab #3 Design and Analysis of CMOS...

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EEE 335 Lab #3 – Basic Gates - Fall 2011 – Yu 1 Lab #3 Design and Analysis of CMOS Gates 2011 Fall Objective: The objective of this lab is to design and develop a library of basic gates. You will be using CADENCE Spectre circuit simulations. These gates will be used in the design a two bit adder and you’ll need 2-input NAND, 2 input NOR, and Inverters. Requirements : 1- Design Section Calculate and pick the device sizes for inverter to have a symmetric t PLH /t PHL . Sweep device sizes to optimize all gates so that they have symmetric t PLH /t PHL . Sweep device sizes to optimize all gates so that they have symmetric rise/fall times Compare the calculation with the spectre simulation results for inverter . 2- For each gate, perform the simulations Select the device sizes with symmetric rise/fall times Simulate the gates and verify their operations. You need to verify every input combination. Plot input and output Measure the rise and fall times. Plot VTC. Find the noise margin for each gate Find the switching threshold VM for each gate 3- Obtain a high-level block symbol of each gate with symmetric rise/fall times Tips: 1. Use Wn =0.45u for inverter and NOR2 gate, Wn=0.9um for NAND2 gate. (Think about why we do

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## This note was uploaded on 02/11/2012 for the course EEE 335 taught by Professor Barnaby during the Spring '09 term at ASU.

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2011Fall_EEE335_Lab3 - Lab #3 Design and Analysis of CMOS...

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