2011Fall_EEE335_Lab4

2011Fall_EEE335_Lab4 - Lab 4 Design and Analysis of Common Source Amplifier with Active Load 2011 Fall 1 Task Design a Common Source Amp with

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Lab # 4: Design and Analysis of Common Source Amplifier with Active Load 2011 Fall EEE 335 Lab #4 Fall 2011 - Yu 1. Task: Design a Common Source Amp with active PMOS load with the following specifications: Technology: CMOS TSMC 0.3 m process (use L=0.3 m for all devices) Power supply: 2.5 V Voltage gain: > 20 dB Total Current: < 1 mA Output dynamic range: > 1.5 V (Please note that the voltage source V 0 is vsin which will have a DC bias voltage as well as an AC signal) 2. Device Parameters: NMOS: tsmc25N: /usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25N.m '2 274.75 / n k A V V th 0.49 V (around this number in Cadence) PMOS: tsmc25P /usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25P.m 95.75 / p k A V V th ≈ - 0.54 V (around this number in Cadence) (Check Page 353 of your textbook for the SPICE model parameter names and units.)
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Lab # 4: Design and Analysis of Common Source Amplifier with Active Load 2011 Fall EEE 335 Lab #4 Fall 2011 - Yu 3. Detailed Tasks: 1). Analysis and Hand Calculation: DC Analysis: Find the proper bias voltages for NMOS and PMOS according to the specifications.
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This note was uploaded on 02/11/2012 for the course EEE 335 taught by Professor Barnaby during the Spring '09 term at ASU.

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2011Fall_EEE335_Lab4 - Lab 4 Design and Analysis of Common Source Amplifier with Active Load 2011 Fall 1 Task Design a Common Source Amp with

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