09_registerscountersrams

09_registerscountersrams - 191 Registers Readings: 7.8-7.9...

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Unformatted text preview: 191 Registers Readings: 7.8-7.9 Storage unit. Can hold an n-bit value Composed of a group of n flip-flops Each flip-flop stores 1 bit of information D Q Dff clk D Q Dff clk D Q Dff clk D Q Dff clk 192 Controlled Register Reset Load Action Q = old Q 1 Q = 1 Q = D D Q Dff clk D Q Dff clk D Q Dff clk D Q Dff clk 193 Shift Register Register that shifts the binary values in one or both directions D Q Dff clk D Q Dff clk D Q Dff clk D Q Dff clk In Out Clock 194 Transfer of Data 2 modes of communication: Parallel vs. Serial Parallel: all bits transferred at the same time Serial: one bit transferred at a time Shift register can be used for serial transfer D Q Dff clk D Q Dff clk 195 Shift Register w/Parallel Load Shift Load Action Q = old Q 1 S h i f t X 1 Parallel Load D Q Dff clk D Q Dff clk D Q Dff clk D Q Dff clk 196 Conversion between Parallel & Serial D3 Q3 4-bit D2 Q2 Shift D1 Q1 Reg. D0 Q0 Shift Load Clk D3 Q3 4-bit D2 Q2 Shift D1 Q1 Reg. D0 Q0 Shift Load Clk LSI LSI 197 Bidirectional Shift Register w/Parallel Load Shift Load Action Q = old Q 1 Parallel Load 1 Shift Up (V*2) 1 1 Shift Down (V/2) D Q Dff clk D Q Dff clk D Q Dff clk D Q Dff clk 198 Counters A reg. that goes through a specific state sequence n-bit Binary Counter: counts from 0 to 2 N-1 in binary Up Counter: Binary value increases by 1 Down Counter: Binary value decreases by 1 3-bit binary up counter state diagram: 199 Binary Up-Counter Imp. 200 Complex Binary Counter Load Count Action Q = old Q 1 Up Count 1 R e s e t 1 1 Load Parallel 201 Arbitrary Sequence Counters Design a 3-bit count that goes through the sequence...
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09_registerscountersrams - 191 Registers Readings: 7.8-7.9...

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