hw2soln - For the following circuits, put them into Product...

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Unformatted text preview: For the following circuits, put them into Product of Maxterms and Sum of Minterms forms. _ $124693 F2.— R+£+D P3 =A§+g+5 a.) F=iiA®B}*C+Di*iA*§+C*D) 1:; 5 +5., gap“ F:/‘TECD+EBCSTABCD+A§CE+A8CD ‘ # ' ‘ +CEEZ‘D1‘CEI365)+Q§BEBD+(EBEIE)+(A§ED) “W59? +<A§CD3+ (A855) +(ABZD) FrCABCD) F = CA+8+C+0\(A-tl3 10(5) (A4B+Z,+Q) (A+§+<+D)CA1B+(+C *C£+B*C+D)<§+B+Ct3)(§ +B¢E+5)<E+Q+C+D)(§+é +05, M 47% 93:4) + A§C5+A§CD _' , fl.” _.—~ ~-‘* “‘0 Rm: a: RED +A Bé-D-fPrBC‘D“/°‘BCD W8C ‘W’flBZS +ABZD mew? --vABCD Cr = CATB+C+036A‘f‘f3-1LWE)(A~-{&flia't§3 )5} “’g“*¢:‘f:? q a”) *Ciwfi rwfixfléarmmweé «who )(iimEiWY/lfifim For the following Verilog code, draw the corresponding Circuit diagram for “bigMod”. Your Circuit should only involve standard gates (AND, OR, NAND, NOR, XOR, Inverter), and the variable names Val, X, Y, and Z. DO NOT SIMPLIFY THE CIRCUIT. Note: all of the code is legal Verilog, with no errors. module tstMod(F, A, B, C); output F; input A, B, C; assign F = A l (B & ~C); endmodule module bigMod(Val, X, Y, Z); output Val; input X, Y, Z; wire T; tstMod Tl (T,X,1,Y); tstMod T2 (Val,Z,T,X); endmodule We wish to implement the following circuit: A jet has 4 engines. Each engine gives a FAIL signal which is TRUE if the engine is broken, and is FALSE if the engine is working fine. The plane can fly as long as at most 1 engine is broken. We want a signal EMERGENCY, which is true if the plane can no longer fly. a.) Would the Sum of Minterms or Product of Maxterms be smaller for this circuit? IL fHSCD FA {safe gem: 1 Per qIK'bL‘? E.“ hé'r‘nvftfi ____...._..M { [DD/’1 :5 jun-{[(f/ l____..a—w b.) Write the Boolean equation for EMERGENCY. It should be in the format identified in 3.3 above (Sum of Minterms or Product of Maxterms, whichever is smaller) h 2: 0+ 3&5 «2; s56 méfo 7‘7 9 ll 3>1 (2) flI Di .1. 3:1 Li Fall : (A’i'B—réi +8+C+5MA+B+E+D> (A-rE-tCncD) (Jigs-(+9) For the circuit given below, Show the output waveform for the transition (A=0,B=1,C=0) to (A=1,B=1,C=0). All gates (inverters, ANDS, 0R5, XORS) have a delay of Ens. Ons 5ns 10115 15115 20115 25ns 3011s 35ns 40ns 45115 50115 55ns 60ns 65ns 70115 NO'fCS CC:- A IAQVC M4J(#:"~d 6’9 U?“ @ bgfildnifl} gflgmg u l-e- QHG’MQ‘IIL‘M uzra‘on 0-? D'- D memml ...
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hw2soln - For the following circuits, put them into Product...

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