lab4 - EE 271 Lab 4 Behavioral Verilog University of...

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EE 271 Lab 4 Behavioral Verilog University of Washington - Department of Electrical Engineering Lab Objectives Implementing designs directly in schematics or structural (gate-level) Verilog can give you the best control, and often the smallest designs. But, sometimes it can be a real pain to optimize all the way down at that level. An alternative is behavioral Verilog, where you tell the CAD tools what you what the output to look like, and it automatically does the Boolean Algebra for you! NOTE: it is easy to design bad behavioral code and forget what hardware it actually creates. So, you may ONLY use behavioral code in this class when SPECIFICALLY told to. In this lab, you may only use behavioral code for the display driver module in the design problem, and the code copied directly from the book for the seg7 code. Assigned Task – Seven-segment display In the class notes we presented a seven-segment display driver. Behavioral code for that seven-segment display is given in Figure 6.38 (page 354) of the book. Enter the code into a new project in Quartus II. Then, create a new module that instantiates the seg7 code twice – one taking an input from SW0 – SW3 and displaying on Hex0 of the board, another taking input from SW4 – SW7 and displaying on Hex1 of the board. Remember that the pin assignment CSV from the website can help you connect your design to specific pins on the board. Note that the 7-segment display on the DE-1 is ACTIVE LOW.
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lab4 - EE 271 Lab 4 Behavioral Verilog University of...

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