lab5 - EE 271 Lab 5 Sequential Logic University of...

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EE 271 Lab 5 Sequential Logic University of Washington - Department of Electrical Engineering Lab Objectives Now that we have mastered combinational logic, it is time to figure out sequential circuits. In this lab you will go through the tutorial on sequential circuits and download a premade design to your board. Then, you get to design your own circuit and get it working. Assigned Task – Mapping sequential logic to the FPGA Read and follow along with the tutorial in chapter C.4 of the book, but use the code shown below instead of the book’s code. Note that you should be able to cut and paste from the PDF. module simple (Clock, Resetn, w, out); input Clock, Resetn, w; output out; reg out; wire [1:0] PS; // Present State reg [1:0] NS; // Next State wire reset; // Here to be consistent with book parameter [1:0] A = 2'b00, B = 2'b01, C = 2'b10; // Next State logic always @(w or PS) case (PS) A: if (w) NS = B; else NS = A; B: if (w) NS = C; else NS = A; C: if (w) NS = C; else NS = A; default: NS = 2'bxx; endcase // Output logic always @(PS) case (PS) A: out = 0; B: out = 0; C: out = 1; default: out = 1'bx; endcase // Switch active-low reset to active-high internally assign reset = ~Resetn; // Stateholding D_FF lsb (PS[0], NS[0], reset, Clock); D_FF msb (PS[1], NS[1], reset, Clock); endmodule
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module D_FF (q, d, reset, clk); output q; input d, reset, clk; reg q; // Indicate that q is stateholding always @(posedge clk or posedge reset) if (reset) q = 0; // On reset, set to 0 else q = d; // Otherwise out = d endmodule You will not be able to follow the simulation part directly. Your goal is to duplicate the inputs shown in C.37 in the simulation. You will also have out, D_FF:msb|q and D_FF:lsb|q instead of z, y~15 and y~14 because the code is different. You will be done after you have explored the output of Timing Analyzer. Print out the Verilog and simulation waveforms.
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lab5 - EE 271 Lab 5 Sequential Logic University of...

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