lab7 - EE 271 Lab 7 Useful Components University of...

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Unformatted text preview: EE 271 Lab 7 Useful Components University of Washington - Department of Electrical Engineering Lab Objectives Over the last 6 labs weve learned how to do most kinds of basic logic, but there are some standard elements that tend to come up over and over again. This lab will help you get some experience with them now, and add them to your toolkit in advance of the final project. Design Problem CyberWar In the last lab we built a simple Tug of War game, and by now youve already crushed your room-mate into submission. Now its the hardwares turn. Your goal is to develop a computer opponent to play against, as well as a scorekeeper that can show exactly how badly it beats you For this lab, everything still uses the rules from lab #6 FSMs via lab #5 style, other logic in structural Verilog or schematics (lab #1 & lab #2 style), though you are allowed to use the seven-segment display driver from lab #4. Counters First off, take your lab #6 and replace the winner system with counters. Specifically, develop a 3-bit counter (holds values 0..7). It starts at 0, and whenever a win comes in to it, it increments its current value by 1. This is a simple FSM. Note that we assume once one player gets to 7 the game is over, so it doesnt matter what happens when a player with 7 points gets one more....
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This document was uploaded on 02/11/2012.

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lab7 - EE 271 Lab 7 Useful Components University of...

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