EE 271 Lab 8
University of Washington - Department of Electrical Engineering
Now that you are an expert logic designer, it’s time to prove yourself.
You have until about
the end of the quarter to do something cool with the DE1 board and your digital design skills.
Note that this lab is MUCH more complex than previous labs, and will take a LOT of time.
Read the entire lab carefully, and START EARLY.
You will need the time!
You will design a significant project on the DE1 board.
In some cases you may want to use
the breadboard as well – note that all of the pins at the bottom of the breadboard are labeled
with the pin they talk to on the FPGA, and thus are usable.
This will be most useful to
people who want to connect up to more interesting inputs and/or outputs for their design,
since all of the digital logic should be done inside the FPGA.
You can access these pins by
having a bus connection “inout [35:0] GPIO_0” to your top-level module (like you used
KEY, SW, LEDR, etc. in other labs).
GPIO_0 is the leftmost connection (A13), and
GPIO_0 is the rightmost connection (L18).
You may code up your design in any style presented in the labs – structural Verilog,
schematics, and/or FSMs in the style of lab #5.
However, you may NOT code up your
design in arbitrary behavioral code – behavioral logic can be used for FSMs (like lab #5), but
that is it.
The only exception is seven-segment display drivers (like lab #4) and similar
modules that convert a number to a picture on an output device – if you are not sure if you
can use behavioral for a specific device, ask before doing it!
You may use the clock_divider circuit if you wish.
However, your ENTIRE circuit should
be based off of EXACTLY ONE clock.
If you need two clock speeds, use the clock divider
to generate the faster clock.
Then, use a counter as a timer to generate an enable signal at the
slower rate – all slower elements will still use the fast clock, but will only change state when
the slower counter signal occurs.
Take a look at the traffic light controller and the timer for
Because this lab is significantly more complex than others, it will be weighted much more
significantly than a normal weekly lab.
You will be graded 100 points on correctness, style, testing, etc.
Your bonus goals is
For each of these projects, there are lots of obvious ways to make it
more useful, more efficient, and more fun.
TAs will give up to 20 bonus points for any of
However, you will get MUCH more credit for a working, simple design than a not-
working, awesome system.
The best plan is to get the basic system working, then add
any frills if/when you have extra time.
Extra Credit - Early Finish