output andOut, orOut;
input A, B;
The top of a module gives the name of the module (AND_OR in this case), and the list of
signals connected to that module.
The subsequent lines indicate that the first two binary
values (andOut and orOut) are generated by this module, and are output from it, while the
next two (A, B) are inputs to the module.
and TheAndGate (andOut, A, B);
or TheOrGate (orOut, A, B);
This creates two gates: An AND gate, called “TheAndGate”, with output andOut, and
inputs A and B; An OR gate, called “TheOrGate”, with output orOut, and inputs A and B.
The format for creating or “instantiating” these gates is explained below.
All modules must end with an endmodule statement.
Simple modules can be built from several different types of gates:
buf <name> (OUT1, IN1); // Sets output equal to input
not <name> (OUT1, IN1); // Sets output to opposite of input
The <name> can be whatever you want, but start with a letter, and consist of letters,
numbers, and the underscore “_”.
Avoid keywords from Verilog (i.e. “module”,
There are multi-input gates as well, which can each take two or more inputs:
and <name> (OUT, IN1, IN2); // Sets output to AND of inputs
or <name> (OUT, IN1, IN2); // Sets output to OR of inputs
nand <name> (OUT, IN1, IN2); // Sets to NAND of inputs
nor <name> (OUT, IN1, IN2); // Sets output to NOR of inputs
xor <name> (OUT, IN1, IN2); // Sets output to XOR of inputs
xnor <name> (OUT, IN1, IN2); // Sets to XNOR of inputs
If you want to have more than two inputs to a multi-input gate, simply add more.
example, this is a five-input and gate: