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Unformatted text preview: ECE 270 Introduction to Digital System Design Fall 2011
TakeHomaWork for Module 1 — Due 8/29/2011 1. [10 points] Using a total of three N—Channel MOSFETS and three Pchannel
MOSFETS, draw a circuit schematic for a threeinput NOR gate. The gate inputs
should be labeled A, B and C, and the gate output should be labeled F. Be sure to
show the power (Vcc) and ground (GND) connections as well. Name: Signature: Your Class N0. is the [cl—st four digits of your PUID followed by the ﬁrst character of your la_st name. ECE 270 Introduction to Digital System Design Fall 2011 2. [10 points] Using a total of three N—channel MOSFETS and three P—channel
MOSFETS, draw a circuit schematic for a twoinput AND gate. The gate inputs
should be labeled A and B, and the gate output should be labeled F. Be sure to show
the power (Vcc) and ground (GND) connections as well. Vcc ECE 270 Introduction to Digital System Design Fall 2011
TakeHomaWork for Module 1 — Due 8/31/2011 1. Assume two hypothetical logic families have the following D.C. characteristics: Logic Family “A” VCC= 5 V l VOH=4.4V VOL: 040 V VIH= 3.60 V l VIL=1.6OV l
VTH = (VOH— VOL)/2 ‘ I0H : ‘4 mA 10L = 4 mA 11H = 0.4 HA l 11L = 0.4 uA l Logic Family “B” Vcc=5V VOH=3.3V lVOL=0.30Vl—VIH=2.6OV VIL=1.6OV l VTH : (VOH‘ VOL)/2 IOH = 400 MA  1OL = 8 m 11H = 40 uA 11L = 0.4 mA ‘ Can gates from family “A” be used to drive gates from family “B”? Explain your answer
by calculating and considering fanout and DC noise margin. Show your work. 6 {3‘
[4 points] Fanout A93 = min \. [4 points] AaB : Lq it” w {52$ iii (if? R ‘2»
~ 5, [2 points] Conclusion: Name: Signature: Your Class N0. is the Last four digits of your PUID followed by the [irst character of your la_st name. ECE 270 Introduction to Digital System Design Fall 2011 2. Given that a (SVolt) CMOS gate’s P—channel output pullup has an “on” resistance of
1609 and that its N—channel output pull—down has an “on” resistance of 809: (a) [4 points] If the desired VOHmin is 4.4 volts and the desired VOLmax is 0.4 volts, what
are the gate’s IOHmax and IOLmax ratings? ,1 _ tr: a
1:3,, 5?» Tiff“ OI “W, "W’ _ aim
IOHmax = w rig/l} mA IOLmax — by); 0 mA (b) [4 points] If a DCNM of 1.2 volts is desired for this CMOS gate family, what do its
VIHmin and VILmaX speciﬁcations need to be, based on the values given in part (a)? w, (r w 1, 2; W A VIHmin = 312, V VILmaX = E}, V (c) [2 points] If the 11H and 11L speciﬁcations for gates in this family are +0.1 mA and
O.1 mA, respectively, what is the practical fanout for circuits constructed using these gates, based on values calculated in part (a)? ,ﬁ 1 , w Mama; 2? (d) [10 points] Show how an LED (with forward voltage VLED = 1.5 V) should be
interfaced to gates in this family to obtain maximum brightness, and calculate the
value of the current limiting resistor required along with its power dissipation. [6 points] Circuit and calculations: 5(«419/5)“ it; (2 M IVE/53:1? 5" 9,5» [2 points] Current limiting resistor value [2 points] Resistor power dissipation = ECE 270 Introduction to Digital System Design Fall 2011 TakeHomaWork for Module 1  Due 9/02/2011 1. A mitjpular CMOS microcontroller is designed to operate over a supply voltage range
of{'l“”pV to Wand at a maximum clock frequency of 100 MHZ (nmnimum clock speciﬁed). The maximum power dissipation over this rangemdfwsupply
voltagégéiiiduclock frequency is speciﬁed to be 400 milliwatts. frequency (a) [10 points] Plot the relationship between power dissipation and supply voltage for
this microcontroller. A 400
B E 300 
‘2; .9 "
a 200
23 E m 100  00 1 2 3 " 4 5 Supply Voltage(V) (b) [10 points] Plot the relationship between power dissipation and clock frequency for
this microcontroller. 400 a — 4 m web 300 — ~~ %:
m
“in?
\ “\E\
“:3
Power Dissmatlon (mW) Name: Signature: Your Class No. is the last four digits of your PUID followed by the first character of your last name. ECE 270 Introduction to Digital System Design Fall 2011 2. Given that a (5volt) CMOS gate’s P—channel output pullup has an “on” resistance of
1209 and that its N—channel output pulldown has an “on” resistance of 609: (a) [4 points] If the desired 10H and 10L are 4 mA (i.e., —4 mA for 10H, +4 mA for 10L), ,
i then the VOH and VOL speciﬁcations for this gate will be: all i gig “Gila a z 3;} M g“; ,5 if” ’“ v0H= 4, E («24 VOL: (b) [2 points] If the VIHmin and VILmax speciﬁcations are 4.2 volts and 0.8 volts,
respectively, then the DCNM for this gate will be: ‘ 2) CA) M ﬁt Lg is g, all, t) g (c) [4 points] If a gate from this family drives a capacitive load of 100 pF, estimate its
rise and fall times. ﬁg} X in i / ‘ z, 1‘ lug X Mi} M} t 7'7 {3,43 it! m, x [Q Rise time estimate = l ns Fall time estimate = ns ECE 270 Introduction to Digital System Design Fall 2011 TakeHomaWork for Module 1 — Due 9/07/2011 Given the following circuit: 7403 (a) [10 points] For the case of BOTH inputs of BOTH gates driven LOW: If the off
state leakage current of each of the 74X03 opendrain NAND gate outputs is +10 HA, and the 11H required by the 74X04 inverter is +500 uA, determine the
maximum value of R that will produce a VIH of at least 4.4 volts at the 74x04 input. MaximumR= I (b) [10 points] For the case of both inputs of ONE gate driven HIGH and both
inputs of the other gate driven LOW: If the 10m,ax of the 74X03 is speciﬁed to be
+8 mA and that the LL required by the 74x04 inverter is O.4 mA, determine the
minimum value of R the will produce a VIL of no more than 0.4 volts at the
74X04 input (assume the same off—state leakage current as Part (a), and round
your answer to the nearest Ohm). ECE 270 Introduction to Digital System Design Fall 2011 (c) [10 points] If you were guest starring on the hypothetical TV series Power of I 02
and you were forced to choose one of these two values (i.e., the “Maximum R”
or the “Minimum R”), which value would you choose, and why? [2 pts] Which value would you pick (circle one): Minimung —or— Maximum Name: Class N0:  Signature: Score: / 30 Your Class No. is the Last four digits of your PUID followed by the first character of your la_st name. ...
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