Mod4_F11_Solns - ECE 270 Introduction to Digital System...

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ECE 270 Introduction to Digital System Design Fall 2011 MOSFET N MOSFET N MOSFET P MOSFET P 5 V X TakeHomaWork for Module 4 – Due October 14 1. [10 pts] Draw the circuit for a bistable using N- and P-channel MOSFETs. 2. [10 pts] Given the following state transition diagram, complete the timing chart below. A B X Y 0 0 10 1 1 01 d1 dd 00 01 10 11 1d 0d d0 A B X Y
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ECE 270 Introduction to Digital System Design Fall 2011 3. [20 pts] Given the following state transition diagram, determine the next state equations it represents in minimum sum-of-products form. X Y A B X* Y* 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 d1 dd 00 01 10 11 1d 0d d0 A B X Y X* = ________________________________________ Y* = ________________________________________ X X B A B A B Y Y Y X X B A B A B Y Y Y 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 Y + A X + B
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ECE 270 Introduction to Digital System Design Fall 2011 TakeHomaWork for Module 4 – Due October 17 1. [20 pts] Complete the timing chart for the edge-triggered flip-flop, below, assuming its t PLH(C Q) is 10 ns and its t PHL(C Q) is 5 ns. Determine the following: (a) [5 pts] the nominal setup time provided for the D flip-flop, based on the excitation signals (D and CLK) depicted in the timing chart: 5 ns (b) [5 pts] the nominal hold time provided for the D flip-flop, based on the excitation signals (D and CLK) depicted in the timing chart: 10 ns (c) [5 pts] the nominal clock pulse width provided for the D flip-flop, based on the excitation signals (D and CLK) depicted in the timing chart: 15 ns (d) [5 pts] the duty cycle of the clocking signal: 50% D CLK Q Q_L 5 ns
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ECE 270 Introduction to Digital System Design Fall 2011 2. [10 pts] Assume a positive edge-triggered D flip-flop (“X”) and a D latch (“Y”) are supplied the signals given on the timing chart, below. Plot the response of each, noting the initial states. NOTE: Assume the propagation delays of the flip-flop and latch are negligible relative to the period of “C”. A X Y C
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ECE 270 Introduction to Digital System Design Fall 2011 TakeHomaWork for Module 4 – Due October 19 1. [10 pts] Given the timing diagram, below, for a state machine that has one input (EN) and two state variables (Q1 and Q0), derive a state transition diagram (note that there is one unused state ). CLK Q1 Q0 EN 00 Q1 Q0 01 EN 10 11 0 0 0 1 1 1
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ECE 270 Introduction to Digital System Design Fall 2011 2. [10 pts] A “new” type of flip-flop, the BU (“Boiler Up”), is described by the following PS-NS table. Derive its next state equation and excitation table. Q* =
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This note was uploaded on 02/12/2012 for the course ECE 270 taught by Professor Staff during the Spring '08 term at Purdue University-West Lafayette.

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Mod4_F11_Solns - ECE 270 Introduction to Digital System...

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