thw_mod4_no2 - duty cycle of the clocking signal: D CLK Q...

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ECE 270 Introduction to Digital System Design Fall 2011 TakeHomaWork for Module 4 – Due October 17 1. [20 pts] Complete the timing chart for the edge-triggered flip-flop, below, assuming its t PLH(C Q) is 10 ns and its t PHL(C Q) is 5 ns. Determine the following: (a) [5 pts] the nominal setup time provided for the D flip-flop, based on the excitation signals (D and CLK) depicted in the timing chart: (b) [5 pts] the nominal hold time provided for the D flip-flop, based on the excitation signals (D and CLK) depicted in the timing chart: (c) [5 pts] the nominal clock pulse width provided for the D flip-flop, based on the excitation signals (D and CLK) depicted in the timing chart: (d) [5 pts] the
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Unformatted text preview: duty cycle of the clocking signal: D CLK Q Q_L 5 ns ECE 270 Introduction to Digital System Design Fall 2011 2. [10 pts] Assume a positive edge-triggered D flip-flop (X) and a D latch (Y) are supplied the signals given on the timing chart, below. Plot the response of each, noting the initial states. NOTE: Assume the propagation delays of the flip-flop and latch are negligible relative to the period of C. A X Y C Name: __________________________________________ Class No: __ __ __ __ - __ Signature: ______________________________________ Score: _______ / 30 Your Class No. is the last four digits of your PUID followed by the first character of your last name....
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This note was uploaded on 02/12/2012 for the course ECE 270 taught by Professor Staff during the Spring '08 term at Purdue University-West Lafayette.

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thw_mod4_no2 - duty cycle of the clocking signal: D CLK Q...

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