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Unformatted text preview: duty cycle of the clocking signal: D CLK Q Q_L 5 ns ECE 270 Introduction to Digital System Design Fall 2011 2. [10 pts] Assume a positive edge-triggered D flip-flop (“X”) and a D latch (“Y”) are supplied the signals given on the timing chart, below. Plot the response of each, noting the initial states. NOTE: Assume the propagation delays of the flip-flop and latch are negligible relative to the period of “C”. A X Y C Name: __________________________________________ Class No: __ __ __ __ - __ Signature: ______________________________________ Score: _______ / 30 Your Class No. is the last four digits of your PUID followed by the first character of your last name....
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- Spring '08
- Logic gate, Flip-flop, Latch, timing chart