thw_mod4_no6

thw_mod4_no6 - ECE 270 Introduction to Digital System...

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ECE 270 Introduction to Digital System Design Fall 2011 1 2 D2 LC 1 2 BQ 1 2 D0 Vcc D1 CLOCK LE LB LG LF Vcc Vcc PALCE26V12 28 2 3 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 1 4 I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/CLK1 I/CLK2 LD Vcc LA ASYNC RESET Vcc TakeHomaWork for Module 4 – Due October 26 1. [20 pts] Given the following circuit based on a 26V12 PLD, complete an ABEL file that implements a 3-bit programmable binary UP counter, i.e., a counter that counts up to the value D 2 D 1 D 0 (entered on DIP switches) and resets to zero. The current state of the counter is displayed as a BCD digit on a 7-segment common anode display. Note that the circuit includes a bounceless switch to provide a clocking signal along with an asynchronous reset (the SPDT pushbuttons are shown in their “normally closed” or “NC” position). Turn in (on separate attached sheets): a. [10 pts] ABEL source file listing b. [10 pts] ispLever Reduced Equations Report
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thw_mod4_no6 - ECE 270 Introduction to Digital System...

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