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Spice2 - ECE 255 ELECTRONIC ANALYSIS AND DESIGN Fall 2011...

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ECE 255 ELECTRONIC ANALYSIS AND DESIGN Fall 2011 S PICE D ESIGN P ROJECT #2 Due: Friday October 21, 2009 5:00 p.m. MSEE 180 Drop Box Design of a Precision Gain Amplifier (Pre-lab for ECE 208 Experiment #5) This exercise will use the PSpice models for Q2N3903 and Q2N3904 npn bipolar junction transistors. The model parameters from Cadence PSpice are given below. .model Q2N3903 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=335.2 Ne=1.208 + Ise=6.734f Ikf=60.26m Xtb=1.5 Br=.8073 Nc=2 Isc=0 Ikr=0 Rc=1 + Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 + Tr=243.9n Tf=300.8p Itf=.4 Vtf=4 Xtf=2 Rb=10) .model Q2N3904 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 + Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 + Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 + Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10) 1. To verify that your models are correct, plot the output characteristics for I B = 20, 40, 60, 80, and 100 µ A for 0 V CE 10 V for both npn bipolar junction transistors to obtain the plots shown below on a single page. Include these plots in your report. The objective is to design a single-transistor amplifier that will meet the following specifications whether a 2N3903 or 2N3904 transistor is used in the circuit. Specifications Voltage gain: out Vs source v A 10 0.5 v = = ± Input impedance: in Z 10k (at mid-frequencies) Output impedance: out Z 2.2k Output voltage swing: out PP v (min) 2V = We would actually like to have an output voltage swing of 3 V PP without distortion. Minimum 3 dB Bandwidth: 30 Hz to 100 kHz Collector Current I B = 20 µ A I B = 20 µ A I B = 40 µ A I B = 40 µ A I B = 60 µ A I B = 60 µ A I B = 80 µ A I B = 80 µ A

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Q1 R1 Rc R2 Re Vcc 6Vdc 0 Vcc Vsin FREQ = 1k VAMPL = .15 VOFF = 0 Vs 0 C1 Rs 1k Vs Vcc Vcc 0 0 C2 R-Load 100k 0 2 N 39 0 3 o r 2 N 39 0 4 Constraints Power supply: V CC = 6 V Source resistance: R S = 1 k Load resistance: R Load = 100 k Capacitor restriction: Maximum of three external capacitors having total capacitance 100 µ F and chosen from the list of standard values given on page 1302 of the text. Resistor restriction: Use nominal 5% values for all resistors (series and parallel combinations are not permitted), see table of standard values on page 1300 of the text. Suggested circuit configuration: NOTE: See sections 13.1, 13.2, and 13.5 of the text for information on transistor amplifiers and sections 13.6 and 13.7 for a detailed discussion of this circuit configuration. A W ORD TO THE W ISE : Spend a few moments trying to achieve a clear view of your objectives, recognize all of the important obstacles, and formulate a coherent plan for obtaining your objective. In particular, take note of the data sheet on the last page.
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Spice2 - ECE 255 ELECTRONIC ANALYSIS AND DESIGN Fall 2011...

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