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ECE 255 ELECTRONIC ANALYSIS AND DESIGN Fall 2011 S PICE D ESIGN P ROJECT #3 Due: Friday, November 18 5:00 p.m. MSEE 180 Drop Box Design of a Common Source Amplifier (Pre-lab for ECE 208 Experiment X) This exercise will use the PSpice model for the J2N3819 n -channel junction field effect transistor. The model parameters for a J2N3819 (from Cadence PSpice) are given below. .model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 + Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u + Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 + Af=1) In addition to the build-in model, you will be using two additional JFET models that you will create to match the maximum and minimum device characteristics given on the 2N3819 data sheet which is attached. Specifically, you will determine the values for Beta and VTO appropriate for the Min and Max values of the Drain-to-Source Saturation Current, I DSS , and Gate-to-Source Voltage, V GS . The equation governing operation in the Beyond-Pinch-Off region is: ( 29 ( 29 2 D GS TO DS I V V 1 V = β - 1. Determine values for Beta and VTO appropriate to complete the following table and list those values (accurate to four significant digits) on the cover page (attached) of your report. I DSS V DS = 15 V V GS @ I D = 200 µ A V DS = 15 V Lambda Beta VTO Min |V P | 2.0 mA –0.5 V 0.003 V –1 Max |V P | 20 mA –7.5 V 0.001 V –1 2. Using the Jbreak elements create two models (one for Min |V P | and the other for Max |V P |) using the three PSpice parameters from the table above. To verify that your models are correct, plot the output characteristics for V GS = 0 and transfer characteristics for each of the three models to obtain the plots shown below. Include these plots in your report. Drain Current
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The objective is to design a single-transistor amplifier that will meet the following specifications whether the 2N3819 transistor or either of the two extreme case models are used in the circuit. Specifications Voltage gain: out Vs source v A 10 v = Input impedance: in Z 100k (at mid-frequencies) Output impedance: out Z 10k < Output voltage swing: out PP v (min) 2V = (i.e., from + 1 V to – 1V) Bias current: I D > 0.4 mA at quiescent point ( Q -point) to enhance linearity Minimum 3 dB Bandwidth: 10 Hz to 100 kHz Constraints Power supply: V DD = 25 V Source resistance: R S = 1 k Load resistance: R Load = 100 k Capacitor restriction: Maximum of three external capacitors having total capacitance 100 µ F and chosen from the list of standard values given on page 1302 of the text. Resistor restriction: Use nominal 5% values for all resistors (series and parallel combinations are not permitted), see table of standard values on page 1300 of the text. Before you begin the design, there is one other critical parameter of the JFET’s that needs to be
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