ECE362 Timing Review

ECE362 Timing Review - ECE 362 Timing Review Need more...

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ECE 362 Timing Review
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Need more memory! What do we do if our 2K of SRAM isn’t enough? Doing complex DSP calculations Large matrix math We need a bigger “scratch pad” Must interface to external memory module!
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The HCS12 Solution… The way that the HCS12 deals with this problem is to use what is called Multiplexed External Bus Interfacing (MEBI) This basically takes the internal data/address bus and sends it out to the Port A and Port B pins. In this way, we are directly connecting the external SRAM to our processor.
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The HCS12 Solution… But why? This seems like a lot of work… We can now, on startup, initialize our micro so that it’s aware of this new memory. This involves writing to various registers (we’ll get to this later) Altogether, this means that we can place our SRAM into the micro’s address space and use it just as we would our embedded
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Memory Hierarchy On the HCS12, the memory spaces are prioritized. External memory has the lowest priority. We should put the external SRAM into the space where other memory doesn’t exist
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Generally (micro signals)… Let’s consider a very general system for external memory interfacing… The micro will send or receive only a few signals Address bus Data bus Read/Write (R/W’) Clock (CLK)
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Generally (micro signals)… Address bus Micro tells the SRAM which address it’s interested in (read or write) Data bus Bidirectional Input to micro on read cycles Output from micro on write cycles
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Generally (micro signals)… R/W’ Micro tells the SRAM whether the current cycle is a read or a write. For a read cycle, R/W’ = 1 For a write cycle, R/W’ = 0 CLK Micro bus clock Is used to generate SRAM control signals combinationally (with the PLD).
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Generally (SRAM signals)… The external SRAM will require certain signals in order to perform its operations. Address bus Data bus OE’ CE’ WE’
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Generally (SRAM signals)… Address bus/data bus are directly connected to the micro. OE’ : Output enable – Tells the SRAM to take control of the data bus and send out the read data. ‘0’ during the second half (CLK = ‘1’) of a read cycle ‘1’ during first half of read cycle and always during write cycles
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Generally (SRAM signals)… WE’ : Write enable – Tells the SRAM to write the data on the data bus to the address on the address bus. The SRAM write occurs on the rising edge
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This note was uploaded on 02/12/2012 for the course ECE 362 taught by Professor Staff during the Spring '08 term at Purdue.

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ECE362 Timing Review - ECE 362 Timing Review Need more...

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