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Unformatted text preview: ECE 362 Outcome 2 Assessment - 1 - Practice Exam / Solution ______________________________________________________________________________ © 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means. PART 1: Multiple Choice – Select the single most appropriate response for each question. Note that none of the above MAY be a VALID ANSWER. Place answers for this part on the supplied BUBBLE SHEET only – nothing written here will be graded. Please REATTACH your completed bubble sheet to this document and TURN BOTH IN TOGETHER – failure to do so will result in a score of ZERO. Do not spend more than 60 minutes on this portion of the exam. (1) A possible consequence of insufficient timing margin is: (A) sensitivity to relative humidity (B) sensitivity to operating temperature (C) sensitivity to switching noise (D) all of the above (E) none of the above (2) An application where internal port pin pull-ups would be useful is: (A) sourcing current to an LED (B) sinking current from an LED (C) driving a CMOS load (D) inputting a switch contact closure to ground (E) none of the above (3) Interrupt servicing latency is defined as: (A) the time it takes to execute an interrupt service routine (B) the time it takes to get to an interrupt service routine once the interrupt request is recognized (C) the time it takes to fetch the first instruction of the interrupt service routine once the interrupt request is asserted (D) the time it takes to clear the device flag once the interrupt request is asserted (E) none of the above (4) The difference between “special” and “normal” HC(S)12 operating modes is: (A) the processor feels better about itself when operating in “special” mode (B) certain registers can be changed only once in “normal” mode, but can be changed any number of times in “special” mode (C) certain registers can only be modified when the processor is running in “special” mode (D) certain registers can be changed only once in “special” mode, but can be changed any number of times in “normal” mode (E) none of the above (5) If memory mapping conflicts occur, the HC(S)12 gives the lowest priority to: (A) register space (B) internal SRAM (C) byte-erasable EEPROM (D) flash EEPROM (E) external memory ECE 362 Outcome 2 Assessment - 2 - Standardized Concept Questions ______________________________________________________________________________ © 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means. (6) On the 9S12C, if an XIRQ request interrupts an IRQ service routine that is in progress, it is referred to as: (A) presumption (B) recursion (C) preemption (D) election (E) none of the above (7) In the logic analyzer experiment (Lab 5), you observed that an instruction was fetched from memory several cycles before it was executed – this is due to the processor’s use of: (A) indirection (B) interrupts (C) pipelining (D) preemption...
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This note was uploaded on 02/12/2012 for the course ECE 362 taught by Professor Staff during the Spring '08 term at Purdue.
- Spring '08