thw_mod2_no2

thw_mod2_no2 - Grading breakdown: (10 points) maximum ECLK...

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ECE 362 Microprocessor System Design and Interfacing Fall 2011 TakeHomaWork for Module 2 – Due Wednesday, October 5 Determine the maximum clock speed a 9S12C128 CPU (5 V) can run at in expanded narrow mode without stretch if a 7C199-10 SRAM is used in conjunction with an LC4032B-5T44C PLD to implement the “glue” logic (round your result to the nearest one-tenth MHz). Note that your determination should include an SRAM read timing margin of 10%. Show your calculations, and draw a detailed, to-scale read timing diagram documenting your results in the space provided below ( 2.0 ns/division ). Use ispLever to perform a timing analysis of the critical read cycle paths and attach pertinent reports (ABEL file to use is in Module 2-B of the Lecture Notes).
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Unformatted text preview: Grading breakdown: (10 points) maximum ECLK speed = _____ MHz (rounded to nearest one-tenth show work) (5 points) timing simulation, ECLK rise to CE assertion for PLD specified = ____ ns (5 points) timing simulation, ECLK rise to OE assertion for PLD specified = ____ ns (5 points) duration of potential bus fighting due to SRAM float delay = ____ ns (25 points) detailed to-scale timing chart, annotated with all pertinent timing parameters Name: ________________________________________ CN: ________________ Score: _____ / 50 ECLK CE OE ADDR/ DATA LA8-15 0 10 20 30 40 50 60 70 80...
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