12_logic - Logic Manipulation Transistors Digital Logic...

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Unformatted text preview: Logic Manipulation Transistors Digital Logic Computers UCSD: Physics 8; 2 What does a computer do? Computers store and manipulate information Information is represented digitally, as voltages Digital format avoids ambiguity below 1.5 V interpreted as 0 (5V CMOS logic) above 3.5 V interpreted as 1 (5V CMOS logic) Information can be manipulated in many ways: can be compared to other information mathematical operations define state of devices (display, speakers, motors, etc.) Transistors: The Main Building Block UCSD: Physics 8; 2 Transistors, as applied to logic designs, act as voltagecontrolled switches n-channel MOSFET is closed when positive voltage (+5 V) is applied, open when zero voltage p-channel MOSFET is open when positive voltage (+5 V) is applied, closed when zero voltage (MOSFET means metal-oxide semiconductor field effect transistor) drain gate source n-channel MOSFET gate p-channel MOSFET source + voltage 5V + voltage drain 5V 0V 5V 5V 0V 0V 0V <5V <5V UCSD: Physics 8; 2 Data manipulation All data manipulation is based on logic Logic follows well defined rules, producing predictable digital output from certain input Examples: AND AB 0 0 0 1 1 0 1 1 C 0 0 0 1 A NOT A C 0 1 1 0 OR AB 0 0 0 1 1 0 1 1 C 0 1 1 1 XOR AB 0 0 0 1 1 0 1 1 C 0 1 1 0 NAND AB 0 0 0 1 1 0 1 1 C 1 1 1 0 NOR AB 0 0 0 1 1 0 1 1 C 1 0 0 0 A B C A B A B A B A B bubbles mean inverted (e.g., NOT AND NAND) UCSD: Physics 8; 2 Logic Gates The logic operations are carried out electronically by gates, represented by the symbols just introduced Gates are constructed out of transistors, typically 46 per gate Transistors simply act like switches, controlling data flow Gate response is typically ~1 nanosecond (1 billionth sec.) Can theoretically build an entire computer using only NAND (or NOR) gates... And then you can take over the world! (sinister laugh...) UCSD: Physics 8; 2 An inverter (NOT) from MOSFETS: 5V 5V A NOT 5V A C 0 1 1 0 0V input output 0V 5V 5V 0V 0V 0V 0 V input turns OFF lower (n-channel) FET, turns ON upper (p-channel), so output is connected to +5 V 5 V input turns ON lower (n-channel) FET, turns OFF upper (p-channel), so output is connected to 0 V Net effect is logic inversion: 0 5; 5 0 Complementary MOSFET pairs CMOS UCSD: Physics 8; 2 A NAND gate from scratch: 5V Both inputs at zero: lower two FETs OFF, upper two ON result is output HI IN A OUT C Both inputs at 5 V: lower two FETs ON, upper two OFF result is output LOW IN A at 5V, IN B at 0 V: upper left OFF, lowest ON upper right ON, middle OFF result is output HI IN B IN A at 0 V, IN B at 5 V: opposite of previous entry result is output HI NAND AB 0 0 0 1 1 0 1 1 C 1 1 1 0 0V A B UCSD: Physics 8; 2 NAND-based gate construction NAND AB 0 0 0 1 1 0 1 1 C 1 1 1 0 NOT A C 0 1 1 0 AND AB 0 0 0 1 1 0 1 1 C 0 0 0 1 invert output (invert NAND) A B NOR OR AB 0 0 0 1 1 0 1 1 C 0 1 1 1 AB 0 0 0 1 1 0 1 1 C 1 0 0 0 invert both inputs invert inputs and output (invert OR) UCSD: Physics 8; 2 Arithmetic Example Let's add two binary numbers: 00101110 = 46 + 01001101 = 77 01111011 = 123 How did we do this? We have rules: 0 + 0 = 0; 0 + 1 = 1 + 0 = 1; 1 + 1 = 10 (2): (0, carry 1); 1 + 1 + (carried 1) = 11 (3): (1, carry 1) Rules can be represented by gates If two input digits are A & B, output digit looks like XOR operation (but need to account for carry operation) XOR A B AB 0 0 0 1 1 0 1 1 C 0 1 1 0 UCSD: Physics 8; 2 Can make rule table: Cin 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 D Cout 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 Digits A & B are added, possibly accompanied by carry instruction from previous stage Output is new digit, D, along with carry value D looks like XOR of A & B when Cin is 0 D looks like XNOR of A & B when Cin is 1 Cout is 1 if two or more of A, B, Cin are 1 UCSD: Physics 8; 2 Binary Arithmetic in Gates A B Cin E D H A B Cin F G Cout + Cout D "Integrated" Chip Input Intermediate Output A B Cin E F H G D Cout 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 Each digit requires 6 gates Each gate has ~6 transistors ~36 transistors per digit UCSD: Physics 8; 2 8-bit binary arithmetic (cascaded) 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 1 0 + + + + + + + + 0 0 0 1 1 0 0 0 1 1 1 1 0 1 1 MSB 00101110 = 46 + 01001101 = 77 01111011 = 123 11 Carry-out tied to carry-in of next digit. "Magically" adds two binary numbers Up to ~300 transistors for this basic function. Also need , , /, & lots more. LSB = Least Significant Bit Integrated one-digit binary arithmetic unit (prev. slide) UCSD: Physics 8; 2 Computer technology built up from pieces The foregoing example illustrates the way in which computer technology is built start with little pieces (transistors acting as switches) combine pieces into functional blocks (gates) combine these blocks into higher-level function (e.g., addition) combine these new blocks into cascade (e.g., 8-bit addition) blocks get increasingly complex, more capable Nobody on earth understands Pentium chip inside-out Grab previously developed blocks and run Let a computer design the gate arrangements (eyes closed!) UCSD: Physics 8; 2 Data Storage Within the computer, data is stored in volatile memory (RAM) essentially charge held on a capacitor also possible to rig two NAND gates to hold one bit called a flip-flop volatile because it goes away when turned off Also store data permanently, usually on magnetic media (floppies, hard drives, tapes) or on optical discs (CD-ROMs, DVDs) information encoded as polarization of magnetic domains older technology used wire coils around ferrite cores (like transformer) to detect/generate magnetic fields UCSD: Physics 8; 2 Example: Flip-Flop Memory Input A: C Outputs NAND AB 0 0 0 1 1 0 1 1 C 1 1 1 0 flip-flop AB 0 0 0 1 1 0 1 1 CD 1 1 1 0 0 1 ? ? Input B: D This simple arrangement of two NAND gates retains a memory: Imagine A and B are in the high state (both 1) C = 0, D = 1 is valid, but so is C = 1, D = 0 can set the state by dropping A or B low momentarily when A and B are restored to high, the previous state is "remembered": e.g., B went low D sticks on 1 Digital Data Everywhere Remote Controls Computer Communications UCSD: Physics 8; 2 Most of today's information is digital Most of today's information is digital Computer communications Cell phone signals TV is moving this way TV remote controls Even our beloved in-class infrared transmitters Today, we'll look at a number examples start with H-ITT transmitter also check out TV remote (actually for stereo) look at serial data communication UCSD: Physics 8; 2 The H-ITT Transmitter Signal When you click your transmitter button: AE: LED indicator comes on, and at same time, TWO bursts of infrared light come out: LED stays on even after transmission stops, until button is released * button: on release of button, LED flashes and two infrared bursts are sent 1st data packet 2nd data packet bursts last 53 milliseconds, are 9 ms apart, and have a bitperiod of about 0.5 ms (about 2000 bits per second) Let's look at it on scope... H-ITT Transmitter Protocol Transmitter 55573 sends an "A" UCSD: Physics 8; 2 first packet second packet Transmitter 55573 sends a "B" first packet second packet UCSD: Physics 8; 2 Comparison of A & B first packets Differences are minor, showing up only near beginning & end We will represent "high" states (light on) as 1's, and lows (off) as 0's Notice standard widths: choices are single- or double-width (both for the zeros and the ones) UCSD: Physics 8; 2 Decoding the A signal Sequence starts out: 01101001001101001001001001... Notice the 01 delimiters: 01101001001101001001001001... This gives the signal its choppy appearance (never see 3 1's or 0's in a row) Actual data appears between delimiters: 1's look fat, 0's look skinny Resulting bit-sequence for A signal (both packets) is: end delimiter 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 button code transmitter ID (normal and inverted) checksum UCSD: Physics 8; 2 The different buttons: first four bits A B C D E << 1001 001 1 first bit always 1 1010 010 2 1011 011 3 1100 100 4 1101 101 5 1110 110 6 UCSD: Physics 8; 2 The Transmitter ID bytes Transmitter number is binary-coded in the usual sense: 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 0 0 0 0 0 0 0 01 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1 Sum is: 32768 + 16384 + 4096 + 2048 + 256 + 16 + 4 + 1 = 55573 this exactly the number pasted behind the battery Second packet inverts all the bits to ensure data integrity UCSD: Physics 8; 2 What's with the Checksum? 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1 1 1 1 1 0 1 1 1 button code transmitter ID (normal first-packet version) checksum Break data into chunks of 8 bits (bytes) and add up: 1001 00000000 11011001 00010101 11110111 Checksums provide a "sanity check" on the data integrity UCSD: Physics 8; 2 Another example using newer remote 1 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 0 0 1 0 0 button code transmitter ID (normal first-packet version) checksum You can use this (first, non-inverted burst) data to verify your understanding Don't look at the answers if you want to challenge yourself first answers on last slide are: button code, transmitter ID, inverted packet contents also check that checksum adds up properly (ignore final "carry" digit) UCSD: Physics 8; 2 Stereo Remote Control Similar to H-ITT transmitters in principle: bursts of infrared light carrying digital information punctuated by delimiters so no long sequences of 1's or 0's Key differences: signal initiated by a WAKE UP! constant-on burst pattern that follows is repeated indefinitely until button is released I can never get fewer than three packets... packet is variable in length depending on button data packet data packet data packet Sample patterns for data packet POWER VOL + VOL - 1 2 3 4 5 6 7 remote ID? data UCSD: Physics 8; 2 000000000 100000000 010000000 100000 010000 110001000 001001000 101001000 011001000 111001000 UCSD: Physics 8; 2 A Different Code... The radio remote uses a different scheme: does not use the 01 delimiters like H-ITT did instead, uses 10 to represent zero, and 1000 to represent 1 sequence for the 5 button is: 100010001000100010001010100010001010001010... ID part 1 1 1 1 1 00 1 1 0 1 00 1 000 data part in data part, least significant bit (LSB) is first so the number part of "5" is 101001000 1010 least significant digit is first, so reverse order for more familiar form: 0101 = 5 UCSD: Physics 8; 2 Serial Communication: Getting the Data Once the H-ITT receiver gets your IR signal, it must communicate this to the computer It does this through the serial port serial refers to the fact that data bits arrive in series (one at a time) alternative is parallel (one wire for each bit), where typically 8 bits (a byte) arrive simultaneously Most digital communications are of serial type IR transmitters! (only one "channel" for light) USB, Firewire ethernet, modems cell phones Parallel sometimes used for printers, but most notably on computer motherboards now 32-bit wide communications is the standard parallel is faster, but more complicated to pull off: lots of wires A look at the H-ITT Serial Datastream E-button on H-ITT (first of two packets): UCSD: Physics 8; 2 10101000011000000000101001101110101010001011110110 Serial datastream looks a lot different this one allows many zeros or ones in a row delimiters (called start bit and stop bit) bracket 8-bit data (1 byte) in this case, 0's are positive voltage, 1's are negative (backwards!) happens much faster than IR: in this case 19,200 bits/sec (baud) Packet breakdown: first packet: button number (5 E), with LSB first: 101000 next three packets are ID, also LSB first within each last packet is checksum type of verification H-ITT bursts 1st data packet serial bursts 2nd data packet UCSD: Physics 8; 2 Wrap-up: Digital Data Everywhere Our world now runs on information and most of this is broken down to binary bit codes for transmission, manipulation, storage Digital advantage is noise immunity very easy to tell a 1 from a 0, even in the presence of environmental noise UCSD: Physics 8; 2 Assignments HW 4 due today Check website for reading assignments HW 5 TBA by end of today Q/O #3 due tomorrow (5/12) by 6 PM B; 249035; 1010.11111100.00110011.00110100.01101101 ...
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