L2 - YORK UNIVERSITY CSE4210 CSE4210 Architecture and...

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1 CSE4210 YORK UNIVERSITY CSE4210 Architecture and Hardware for DSP Lecture 2 Fast Addition CSE4210 YORK UNIVERSITY Fast Addition • Carry-Lookahead Adders • Carry Select Adders • Conditional Sum Adders •Ca
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2 CSE4210 YORK UNIVERSITY Carry Lookahead Adders 1 1 0 0 1 2 1 0 1 2 1 2 1 0 0 2 1 0 1 1 2 2 2 2 3 1 0 0 1 0 1 1 1 1 2 0 0 0 1 1 + + + + + = + + + = + = + + = + = + = + = = = = n n n n n n i i i i i i i i i i i i i P P P C P P P G P G G C P P P C P P G P G G P C G C P P C P G G P C G C P C G C C P G C C P S B A P B A G " " " CSE4210 YORK UNIVERSITY Carry Lookahead Adders • Time = Carry generate/propagate + carry lookahead (to generate C’s)+ sum (EXOR) = 3+2+2=7 gate delays. • The problem is we need n-input AND, for 32 or 64-bit numbers that is not practical.
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3 CSE4210 YORK UNIVERSITY Carry Lookahead Adders CSE4210 YORK UNIVERSITY Carry Lookahead Adders • In order to limit the fan-in in the carry generation circuitry, we use block carry lookahead adders. • Consider for examples the number is divided into blocks each of 4 bits. • That means the fan-in will be limited to 4 (not 5) • Each block has a block carry generate G* and block carry propagate P*
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4 CSE4210 YORK UNIVERSITY Carry Lookahead Adders G 0 G 1 G 2 G 3 P 0 P 1 P 2 P
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L2 - YORK UNIVERSITY CSE4210 CSE4210 Architecture and...

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