L3 - YORK UNIVERSITY Verilog Review and Fixed Point...

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1 YORK UNIVERSITY Verilog Review and Fixed Point Arithmetics Mokhtar Aboelaze based on slides by Dr. Shoab A. Khan CSE4210 Winter 2012 YORK UNIVERSITY Overview • Floating and Fixed Point Arithmetic • System Design Flow – Requirements and Specifications (R&S) – Algorithmic Development in Matlab and Coding Guidelines • 2’s Complement Arithmetic • Floating Point Format • Qn.m format for Fixed Point Arithmetic • Addition, Multiplication and Scaling in Qn.m • LTI systems and implementation in Qn.m format
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2 YORK UNIVERSITY Floating & Fixed Point Arithmetic • Two Types of arithmetic Floating Point Arithmetic • After each arithmetic operation numbers are normalized • Used where precision and dynamic range are important • Most algorithms are developed in FP – Ease of coding • More Cost (Area, Speed, Power) Fixed Point Arithmetic • Place of decimal is fixed • Simpler HW, low power, less silicon • Converting FP simulation to Fixed-point simulation is time • consuming • Multiplication doubles the number of bits – NxN multiplier produces 2N bits • The code is less readable, need to worry about overflow and scaling issues YORK UNIVERSITY System Design Flow and Fixed Point Arithmetic
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3 YORK UNIVERSITY System Design Flow The requirements and specifications of the application are captured The algorithms are then developed in double precision floating point format – Matlab or C/C++ A signal processing system general consists of hybrid target technologies – DSPs, FPGAs, ASICs For mapping application developed in double precision is partitioned into – hardware & software Most of signal processing applications are mapped on Fixed-point Digital Signal Processors or HW in ASICs or FPGAs The HW and SW components of the application are converted into Fixed Point format for this mapping YORK UNIVERSITY Requirements & Specifications 12V DC nickel metal hybrid, nickel cadmium or lithium-ion battery pack Handheld >10,000 hours MTBF <30 min MTTR Reliability 2ppm or better Frequency Stability >55 dB Harmonic Suppression <60 dB Spurious Emission 2W Output Power Specifications Characteristics •Gathering R&S is the first step of the system design •System components and algorithms are then selected that meet the requirements •Example R&S of a UHF Radio are shown
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4 YORK UNIVERSITY R&S of a UHF Radio (cont) Radio works as SDR and should be capable of accepting additional waveforms Waveforms > 600 hops/s, frequency hopping on full hopping band Frequency hopping Turbo codes, convolution, Reed–Solomon FEC OFDM supporting BPSK, QPSK and QAM Modulation Multi-path with 15 μ s delay spread and 220 km/h relative speed between transmitter and receiver Channel Up to 512 kbps multi-channel non-line of sight Data rate 420 MHz to 512 MHz Frequency Range Specifications Characteristics YORK UNIVERSITY Algorithm Development and Mapping • The R&S related to digital design are forwarded to
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This note was uploaded on 02/13/2012 for the course CSE 4111 taught by Professor Edmonds during the Winter '12 term at York University.

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L3 - YORK UNIVERSITY Verilog Review and Fixed Point...

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