L4_it_bound - YORK UNIVERSITY CSE4210 Chapter 2 Iteration...

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1 YORK UNIVERSITY CSE4210 Chapter 2 Iteration Bound Mokhtar Aboelaze CSE4210 Winter 2012 YORK UNIVERSITY CSE4210 Discrete Real Time Systems • A discrete real time system usually is a continuously running program that receives some input and produce an output. • In many designs, data is processed in fixed size chunks. • The system should be fast enough to complete processing a chunk before it acquires the next one. • Usually, an analog signal is captured, digitized and then processed by a CPU, DSP of FPGA
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2 YORK UNIVERSITY CSE4210 Discrete Real Time Systems • The system could be a single rate or multirate. • In a single rate system, the number of samples per second at the input and output of the system is the same. • In a multi rate system, that number is different. • For example in a digital front end of a receiver, the samples go through multiple stages of decimation decreasing the number of samples per second in every stage. Transmitter if the opposite YORK UNIVERSITY CSE4210 Representation of DSP Algorithms • Many ways to represent DSP algorithms • Kahn Process Network • Data flow graph • Signal flow graph • Dependence Graph
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3 YORK UNIVERSITY CSE4210 Kahn Process Network • KPN is a set of concurrently running autonomous processes. • Processes communicate among themselves in a point-to-point manner over unbounded buffers. • A process may read from a buffer, process data, and write the result to another buffer. • Reading is a blocking operation, writes are non-blocking YORK UNIVERSITY CSE4210 Example of a LPN P 1 P 3 P 4 P 2
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4 YORK UNIVERSITY CSE4210 JPEG as KPN Source RGB- YCbCr DCT Quantization Entropy Coding Sink YORK UNIVERSITY CSE4210 Limitations on KPN • Reading is done from a FIFO, some DSP algorithms requires non FIFO reading (FFT). • Once the data is read from the fifo, it is gone, some applications require multiple reading of the same data • All values written in a FIFO will be read, some algorithms may not read all the values produced by a process.
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5 YORK UNIVERSITY CSE4210 Representation of DSP Algorithms • Block Diagram Y(n)=b 0 x(n)+b 1 x(n 1)+b 2 x(n 2) Z -1 Z -1 y(n) x(n) b 0 b 1 b 1 YORK UNIVERSITY CSE4210 Representation of DSP Algorithms • Signal Flow Graph y(n) x(n) b 0 b 1 b 1 Z -1 Z -1
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6 YORK UNIVERSITY CSE4210 Representation of DSP Algorithms A B A B y(n) x(n) (2) (4) (2) (4) DFG Synchronous DFG 1 1 1 1 D Data Flow Graph Sometimes represented as a dot YORK UNIVERSITY CSE4210 Representation of DSP Algorithms •D FG – Nodes represents computations (functions) and directed edges represent data paths (communication). – Associated with every node its execution time (in parenthesis), – Edges have a non-negative delay – Nodes can fire (perform the computations) if all input data are available.
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7 YORK UNIVERSITY CSE4210 Representation of DSP Algorithms • Imposes a constraints on the DFG.
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This note was uploaded on 02/13/2012 for the course CSE 4111 taught by Professor Edmonds during the Winter '12 term at York University.

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L4_it_bound - YORK UNIVERSITY CSE4210 Chapter 2 Iteration...

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