Lab 2
CSE4210
Winter 2012
Dept. of Computer Science and Engineering
CSE4210 – Architecture and Hardware for DSP
Lab 2
Floating Point Multipliers
Introduction
This lab will introduce you to floating point numbers. You will be asked to design
a floating point multiplier, then you have to reduce (not necessarily minimize)
the clock cycle of a circuit that uses the multiplier by using pipelining.
In the lecture, we studies IEEE754 standard for floating point representation. In
this lab, we will introduce a simpler format for FP representation that allows you
to design a multiplier and reduce the clock cycle time.
In this lab, we use a total of 18 bits to represent a floating point number.
The format of the number is as follows
Sign bit
: 1 bit for sign. 0 means positive, 1 means negative
Exponent
: 8 bits for exponent, with a bias of 127
Mantissa
: 9 bits for the mantissa.
We will be implementing all the features in IEEE754, there is no NaN, infinite, or
denom. We assume that the most significant bit of the mantissa is always 1, and
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 Winter '12
 Edmonds
 Computer Science

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