Verilog - Chapter 2 Using Hardware Description Language...

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1 Chapter 2 Using Hardware Description Language Verilog Mokhtar Aboelaze based on slides by Dr. Shoab A. Khan CSE4210 Winter 2012 Overview • Algorithm development isa usually done in MATLAB, C, or C++ • Code must be structured such that H/W and S/W designers can correlate various components • H/W is written in Verilog (or any other HDL). • SystemVerilog enhances some of the features of Verilog for design, but more importantly for verification
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2 Verilog – An Overview • “Though Verilog is C like in syntax but has distinct character and interpretation. A programmer must set his perception right before coding in Verilog. He must visualize hardware in his mind while structuring Verilog modules consisting of procedural blocks and assignments.” • Some constructs in Verilog is for supporting verification, modeling, and simulation and do not synthesize (RTL Verilog is synthesizable). System Level Design Algorithm Development Design Specification Floating Point Behavioral Description S/W – H/W Partitioning S/W – H/W Co-verification S/W Fixed Point Implementation S/W System Integration & Testing Hardware Development and Testing H/W Fixed point conversion RTL Verilog Implementation Functional Verification Synthesis Gate level netlist layout Timing & Functional Verification Software development and testing System level design verification and testing
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3 Verilog • A Verilog code has a top level module which may instantiate many other modules. • The module is the basic building block in Verilog • A module when synthesized infers digital logic. • The designer conceives the design as hierarchically interconnected lower level modules forming higher level modules • Each module starts with the keyword module , followed by the module name and parameters list. The module is ended with the keyword endmodule . Modules module FA (<port declaration>); . . . endmodule module FA ( input a, Input b, input c_in, output sum, output c_out); assign {c_out,sum} = a+b+c_in; endmodule
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4 RTL Design • At RTL level the designer must know all the registers in the design • The computations performed are modeled by a combinational cloud • Gate level details are not important • HDLs Verilog/VHDL are used to implement a design at RTL level • Verilog resembles with C and is usually preferred in industry RTL Design
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5 Verilog Standards • 1995: IEEE Standard 1364-1995 (Verilog 95) • 2002: IEEE Standard 1364-2001 (Verilog 2001) • 2003: IEEE Standard 1364-2001 revision C • 2005: IEEE Standard 1364-2005 (Verilog 2005) “1364-2005 IEEE Standard for Verilog Hardware Description Language” • 2005: IEEE Standard 1800-2005 (SystemVerilog) “1800-2005 IEEE Standard for System Verilog: Unified Hardware Design, Specification and Verification Language Design Partitioning • If possible partition such that boundaries reside at register outputs.
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This note was uploaded on 02/13/2012 for the course CSE 4111 taught by Professor Edmonds during the Winter '12 term at York University.

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Verilog - Chapter 2 Using Hardware Description Language...

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