cs1104-p2-06

cs1104-p2-06 - CS1104: Computer Organisation

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Unformatted text preview: CS1104: Computer Organisation http://www.comp.nus.edu.sg/~cs1104 School of Computing National University of Singapore CS1104-P2-6 Processor: Datapath and Control 2 PII Lecture 6: Processor: Datapath and Control Datapath: Single-bus Organization Multiple-bus Organization MIPS: Multicycle Datapath and Control Stages of Instructions Datapath Walkthroughs Processor and Logic Design CS1104-P2-6 Processor: Datapath and Control 3 PII Lecture 6: Processor: Datapath and Control Reading: Chapter 9 of textbook, which is Chapter 7 in Computer Organization by Hamacher, Vranesic and Zaky. Optional reading: Chapter 5 in Computer Organization & Design by Patterson and Hennessy. CS1104-P2-6 Processor: Datapath and Control 4 Datapath CS1104-P2-6 Processor: Datapath and Control 5 Recap: Organisation Processor Control Datapath Memory Devices Input Output Cache Registers Bus CS1104-P2-6 Processor: Datapath and Control 6 Fundamental Concepts Processor (CPU): the active part of the computer, which does all the work (data manipulation and decision-making). Datapath: portion of the processor which contains hardware necessary to perform all operations required by the computer (the brawn). Control: portion of the processor (also in hardware) which tells the datapath what needs to be done (the brain). CS1104-P2-6 Processor: Datapath and Control 7 Fundamental Concepts (2) Instruction execution cycle: fetch , decode , execute . Fetch: fetch next instruction (using PC) from memory into IR. Decode: decode the instruction. Execute: execute instruction. Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction CS1104-P2-6 Processor: Datapath and Control 8 Fundamental Concepts (3) Fetch : Fetch next instruction into IR (Instruction Register). Assume each word is 4 bytes and each instruction is stored in a word, and that the memory is byte addressable. PC (Program Counter) contains address of next instruction. IR [[PC]] PC [PC] + 4 CS1104-P2-6 Processor: Datapath and Control 9 Single-bus Organization Data line Address line PC MAR MDR Y Internal processor bus Memory bus Z MUX A ALU B Constant 4 Select Add Sub XOR : ALU control lines Carry-in IR RO R( n 1) : : TEMP Instruction decoder and control logic . . . Control signals CS1104-P2-6 Processor: Datapath and Control 10 Instruction Execution An instruction can be executed by performing one or more of the following operations in some specified sequence: Transfer a word of data from one register to another or to the ALU (Arithmetic Logic Unit). Perform an arithmetic or a logic operation and store the result in a register....
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This note was uploaded on 02/09/2012 for the course CSCI 504 taught by Professor Jon during the Spring '11 term at IUP.

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cs1104-p2-06 - CS1104: Computer Organisation

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