Written Assignment 2 - • Each of the 2 inverter gates has...

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Shayan Rizvi Written Assignment 2 CSE 2300 1. K-map XY= 00 XY= 01 XY= 11 XY= 10 0 0 2 0 6 1 4 1 1 1 3 1 7 0 5 1 Z =0 Z = 1 2. K-map XY = 00 XY = 01 XY = 11 XY = 10 0 0 2 1 6 0 4 1 1 1 3 0 7 1 5 0 C = 0 C = 1 X (XOR) Y (XOR) C 2 logic gates were used which were 2 XOR gates K-map XY = 00 XY = 01 XY = 11 XY = 10 0 0 2 0 6 1 4 0 1 0 3 1 7 1 5 1 C = 0 C = 1 4 logic gates were used which were 2 XOR gates, one OR gate and one AND gate 3.
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a) Figure 1 Above is what the circuit looks like A B C D E F 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1
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0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 Table 1 The table above (table 1) is the truth table for the equation b)
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Figure 2 Above is what the circuit looks like made with only NAND and Inverter gates There were 6 NAND gates and each gate uses 4 transistors There were 2 inverter gates and each gate uses 2 transistors 28 transistors used With each of the 6 NAND gates has a delay of 1.4 ns
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Unformatted text preview: • Each of the 2 inverter gates has a delay of 1 ns • • Total delay was 10.4 ns c) Figure 3 Shows the circuit implemented with NOR and Inverter gates • There were 8 Inverter gates and each gate used 2 transistors • There were 6 NOR gates and each used 4 transistors • • There were a total of 40 transistors used • Each of the 8 Inverter gates has a delay of 1 ns • Each of the 6 NOR gates has a delay of 1.4 ns • • The total delay was 16.4 ns...
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This note was uploaded on 02/14/2012 for the course CSE 2300 taught by Professor Stevechu during the Fall '11 term at Central Connecticut State University.

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Written Assignment 2 - • Each of the 2 inverter gates has...

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