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Unformatted text preview: • Each of the 2 inverter gates has a delay of 1 ns • • Total delay was 10.4 ns c) Figure 3 Shows the circuit implemented with NOR and Inverter gates • There were 8 Inverter gates and each gate used 2 transistors • There were 6 NOR gates and each used 4 transistors • • There were a total of 40 transistors used • Each of the 8 Inverter gates has a delay of 1 ns • Each of the 6 NOR gates has a delay of 1.4 ns • • The total delay was 16.4 ns...
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This note was uploaded on 02/14/2012 for the course CSE 2300 taught by Professor Stevechu during the Fall '11 term at Central Connecticut State University.
 Fall '11
 SteveChu

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