Blackfin BF533 DSP's Architecture

Blackfin BF533 DSP's Architecture - Microcomputer Systems 1...

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Unformatted text preview: Microcomputer Systems 1 Blackfin BF533/2/1 DSPs Architecture February 16, 2012 Veton Kpuska 2 Blackfin ADSP-BF533/2/1 Architecture Overview Core Registers ALU, MAC, Shifter Data Addressing Modes Program Sequencer Event Controller Peripherals Instruction Set Overview Memory Architecture Cache February 16, 2012 Veton Kpuska 3 Blackfin Architecture Details Blackfin Core Details Registers ALU, MAC, Shifter Sequencer, Pipeline, Event Controller Blackfin Memory Memory Architecture Cache Peripherals General Peripherals: Parallel Peripheral Interface (PPI) Serial Ports (SPORTs) Serial Peripheral Interface (SPI) General Purpose Timers Universal Asynchronous Receiver Transmitter (UART) Twin-Wire Interface (TWI) Real Time Clock (RTC) Watchdog Timer (WDT) Ethernet, CAN DMA Peripherals listed in Blue are included in BF531/532/533 Family Peripherals listed in Blue are included in BF531/532/533 Family February 16, 2012 Veton Kpuska 4 Features Integrated instruction set architecture Single instruction set for signal processing and control Programmable interrupt levels Real-time tasks get the highest priority level Memory protection with an MMU Regions of memory can be protected from access Networked peripherals in addition high speed connectivity to ADC, DAC and video peripherals Unified address space and byte addressable Support for User and Supervisor modes Robust ALU including both signal processing functions as well as traditional MPC/MPU functions February 16, 2012 Veton Kpuska 5 ADSP-BF533 Processor February 16, 2012 Veton Kpuska 6 Processor Core Architecture 2 16-bit Multipliers 2 40-bit Accumulators 2 40-bit Arithmetic Logic Units (ALU) 1 40-bit Shifter 4 8-bit Video ALUs Data Arithmetic Unit Performs Operations on 8-bit, 16-bit, & 32-bit data From Register File: 8 32-bit Registers R0-R7 Computational Units 2 ALUs 2 MAC Shifter Set of Video ALUs February 16, 2012 Veton Kpuska 8 Computational Units Data Arithmetic Unit A1 40 barrel shifter A0 40 16 16 8 8 8 8 LD0 32-bits LD1 32-bits SD 32-bits R0 R1 R2 R3 R4 R5 R6 R7 R0.L R1.L R2.L R3.L R4.L R5.L R6.L R7.L R0.H R1.H R2.H R3.H R4.H R5.H R6.H R7.H February 16, 2012 Veton Kpuska 9 Data Formats ADSP-BF53x processors are primarily: 16-bit Fixed-point machines. Most operations are in Twos complement number representation, others are Unsigned numbers, and Binary strings Additional instructions support 32-bit integer arithmetic 8-bit arithmetic and block floating point....
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Blackfin BF533 DSP's Architecture - Microcomputer Systems 1...

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