Suhas's Lab

Suhas's Lab - EE 3221 Suhas Patel June 16, 2004 ‘...

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Unformatted text preview: EE 3221 Suhas Patel June 16, 2004 ‘ Objective: To study the input and output characteristics of bipolar and FET follower circuits. Circuit Diagrams: A 8 tan Imgn Fig la 10v 3 to m A OtD-IOV eta-10v Fi 2a 9 _:_ my Fig 2:: mm In a 10kt! A oto—Iov Flg3 Procedures: The procedures for this experiment were the same as given in the lab manual. Observations: Part 1 Data: Bl] V9.9 .45 A V M1] (9.9. 45 Part 3 Data: Part 5 Data: i--ii-nfiqi-ihas\pspice\lab#2—SCHEMATIC1—simulationsetting.out 06/23/04 19:06:11 // Suhas Patel // Experiment 2 — PSPICE Assignment *Analysis directives: S i .TF V([OUTPUT]) V_V1 .PROBE 95pm Assxewmm **** INCLUDING lab#2-SCHEMATIC1-net **** * source LAB#2 .EXTERNAL OUTPUT Output Q‘Ql N00050 N000030 N00082 Q2N3904 Q_QZ N00050 N00082 OUTPUT QZN3904 V_V1 N00116 0 DC 5Vdc AC 5V V V2 N00050 0 12V R—Rl N00116 N000030 1k 3333 3333333 33* — Vomcst Faflowex" **** RESUMING 1ab#2~SCHEMATICl—simulationsetting.sim.cir **** u _ u 0 . mc lab#2 SCHEMATICI . als c ‘K“‘+s **** INCLUDING lab#2-SCHEMATIC1.als **** .ALIASES Q_Q1 Ql(c=N00050 b=N000030 e=N00082 ) Q_QZ Q2(c=N00050 b=N00082 e=OUTPUT ) V_V1 V1(+=N00116 —=0 ) V_V2 V2(+=N00050 —=O ) R_R1 R1(1=N00116 2=N000030 ) R_R2 R2(1=O 2=N00082 ) R_R3 R3(1=0 2=OUTPUT ) _ _(Output=OUTPUT) .ENDALIASES **** RESUMING lab#2—SCHEMAIIC1—simulationsetting.sim.cir **** .END D H“ 06/23/04 19:02:51 *HHHHH Evaluation PSpice (Nov 1999) HHHHHHH ** Profile: "SCHEMAIICl—simulationsetting" [ C:\Suhas\pspice\lab#2~SCHEMATIC1—simulationsetting.Sim ] **** BJT MODEL PARAMETERS **********************************************************************t******* QZN3904 NPN IS 6.734000E-15 BF 416.4 NF 1 VAF 74.03 IKF .06678 153 6.734000E-15 NE 1.259 BR .7371 NR 1 RB 10 RC 1 CJE 4.493000E—12 MJE .2593 CJC 3.638000E—12 MJC .3085 TF 301.200000E—12 XTF 2 VTF 4 ITF .4 Pace: 1 As\pspice\lab#2—SCHEMATIC1—simulationsetting.out 06/23/04 19:06:11 TR 239.500000E-09 XTB 1.5 CN 2.42 D .87 *****i******** ’*** 06/23/04 19:02:51 *********** Evaluation PSpice (Nov 1999) ** Profile: "SCHEMATIC1—simulationsetting" [ C:\Suhas\pspice\1ab#2—SCHEMAIIC1—simulationsetting.Sim 1 **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C 'q "r '. *t******ink*i'i'iri'i'******1-***************i~*****************i'i'i-t‘ki-‘kiziicii'i't‘ki-irink*:*fl 1 £7.41! NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE (N00050) 12.0000 (N00082) 4.3537 (N00116) 5.0000 (OUTPUT) 3.6561 (N000030) 4.9965 ‘ VOLTAGE SOURCE CURRENTS NAME CURRENT v_v1 -3.514E—06 [v2 —4. 088E—03 TOTAL POWER DISSIPATION 4.91E-02 WATTS SMALL-SIGNAL CHARACTERISTICS V(OUTPUT)/V;V1 = 9.853E'01 INPUT RESISTANCE AT V~V1 = 1.371E+06 OUTPUT RESISTANCE AT V(OUTPUT) = 7.749E+00 JOB CONCLUDED TOTAL JOB TIME .03 Page: 2 ...
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Suhas's Lab - EE 3221 Suhas Patel June 16, 2004 ‘...

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