cadence_TUT_2 - EE456 Lab Tutorial 2 EE456 Lab Tutorial 2...

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EE456 Lab Tutorial 2 EE456 Lab Tutorial 2 Cadence HSPICE Simulation Introduction 1.0 Introduction The purpose of the second lab tutorial is to help you in simulating your inverter design that you designed in the first lab tutorial. You will create a hierarchical design, i.e., use the inverter symbol that you generated in another schematic in this design. You will also use HSPICE to simulate your design and evaluate its performance by examining the simulation results. Upon completion of this tutorial, you should be able to: - Do a hierarchical design using cells that you have designed - Use buses and tap wires from buses. - Simulate your schematic using HSPICE - Examine the results of your HSPICE simulation 1.1 Getting started Copy the hspice.include file in the /package/cae/cadence/cells/tsmc025 directory to your home directory. Use any text editor to view the contents of the file. The file includes various process corners that will be used for simulation. To select a particular process corner, uncomment (remove the * ) the .LIB line corresponding to the supply voltage and process corner you wish to use. For this tutorial we will be using the 2.5V typical model process corner. A process corner is a simulation environment that represents some set of operating conditions that the designer is concerned about. 2.0 Create a New Schematic to be Simulated Under the same library (tutorial), create a new cellview named InverterTest . Use the Add Instance command to place your inverter symbol in the cellview. It should be found under the tutorial library. 1
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EE456 Lab Tutorial 2 Use the Add Instance command to place two capacitors in the cellview from the analogLib library and give them a value of 10fF (when you type in the value in the property window, just type 10f) . For this tutorial, we will create two bit wide buses for input, internal nodes and output. To add a bus, click the Wire (wide) icon. Draw the bus as you would draw any normal (narrow) wire. After creating the bus, the bus must be named. The same command to add wire names for narrow wires is used, however the syntax for naming the bus is slightly different. Bus names is in the form Name < a : b > , where a and b denotes the range of bits of the bus. Several two bit buses that will be created in this tutorial include In<0:1> , internal<0:1> and Out<0:1> . Similar to the previous tutorial, it is possible to add several names to different buses at one time. To do this, make sure the Bus Expansion button is off and simply type the names of the buses separated by a space in the Names field. The names will be added in order when you click on the various nets. As an exercise, create and name the buses similar to the ones in the final schematic. To draw or tap wires to and from the buses, draw wires from the buses and name them correspondingly to their bits. To name the individual bit lines, type in the bus name (e.g. In<0:1> or simply <0:1> ) and turn on Bus Expansion in the Add Wire Name window. The Bus Expansion button is used to extract individual bit names from the bus. When you start placing the names on the wires, you will
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This note was uploaded on 02/19/2012 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue.

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cadence_TUT_2 - EE456 Lab Tutorial 2 EE456 Lab Tutorial 2...

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