week5

# week5 - Interconnects Assume 3 line divide them into equal...

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Interconnects Assume 3 line : divide them into equal sections high resistance small capacitance high inductance high impedance line (inductive) high capacitance small resistance small inductance low impedance line (capacitive) When you apply a signal ( sharp step function) Capacitance lines are suitable for power distribution They kill the signal. delay due to finite length delay due to RLC charging more suitable for signal

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Line capacitance C = ε di di t WL d A e = first order approximation As you go to deep submicron, make L , but to reduce resistance you make H Submicron interconnect C wire = C pp + C fringe = ) / log( 27 2 / H t t H W di di di e + - : be careful using this formula L W H t di Oxide H W fringe field W H t di field fringe field C due to fringe field 1 W/t di or W/H 1pF/cm
Table 4.2 (page 143) gives average capacitance between PP(parallel plate) and fringe. Different interconnects in 0.25 μ process Poly – field oxide high capacitance Metal – active > metal – field oxide Table 4.3(page 144) gives interwire capacitance on same level. Resistance HW L R r = ? : resistivity ( cm) , H : constant W L R R ¦ = R ? : sheet resistance(( /cm) Silicide and polycide are used to reduce sheet resistance of diffusion/poly layers. n + , p + n + , p + + silicide Poly Polycide Al R ? 50 ~ 150 3 ~ 5 150 ~ 200 4 ~ 5 0.05 ~ 0.1 Unlike metal Si 2 W and Si 2 Ti can stand high temperature processing. Metal

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## This note was uploaded on 02/19/2012 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue.

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week5 - Interconnects Assume 3 line divide them into equal...

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