week6 - VDD CMOS inverter VDPMOS S G ID- D Vin VGS- Vout D...

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CMOS inverter V GSn = V in I Dn = I D V GSp = V in – V DD I Dp = I D V DSn = V out V DSp = V out – V DD I DSp = -I DSn V DD V DD V out V out R n R p V in = V DD V in = V DD V in = 0 Direct path to ground V out = 0 Direct path to V DD V out = V DD V out V DD I DN PMOS NMOS V out V in NMOS off PMOS Res NMOS Sat PMOS Res NMOS Sat PMOS Sat NMOS Res PMOS Sat NMOS Res PMOS off V DD V in G S D D S V out C L V D - I D - V GS - V D + I D + V GS + PMOS NMOS
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CMOS inverter / Static Behavior Switching threshold V M Both PMOS and NMOS are in velocity saturation I DN +I DP = 0 ignoring channel length modulation ( I ) 0 2 2 = - - - + - - Dsatp Tp D M Dsatp p Dsatn Tn M Dsatn n V V V V V K V V V V K solving for V M r V V V r V V V Dsatp Tp DD Dsatn Tn M + + + + + = 1 2 2 , N satn P satp Dsatn n Dsatp p W W V K V K r u u = = For large V DD r rV V DD M + = 1 , r=1 V M =V DD /2 equal noise margins For long channel devices NMOS and PMOS transistors in saturation V M – V T < V Dsat ( I ) & 0 ) ( ) ( 2 2 = + - + - DD TP M p n T M n V V V K V V K r V V r V V Tp DD Tn M + + + = 1 ) ( , n p K K r - = For 0.25u CMOS ( I ) 5 . 3 2 / 2 / ' ' / / = + + - - - = Dsatp Tp M DD Dsatn Tn M Dsatp Dsat P N N N P P V V V V V V V V n V K K L W L W V M 2.5V 1.25V 1 3.4 10 W P /W N
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Sometimes you don’t want symmetry noise on the Gnd plane So you adjust (W/L)P/(W/L)N ratio to get nonsymmetric V M . But as can be seen from figure V M does not change a lot with the ratio. Noise Margin Other than threshold voltage, we are interested in knowing the noise margins. g V V V DD IL IH - = - , g V V V M M IH - = , g V V V V M DD M IL - + = g V V V V V NMH M M DD IH DD + - = - = , g V V V V NML M DD M IL - + = = To find the gain, we need to take into account the channel length modulation otherwise gain V in V out t V in t V out t V out V OL V out V OH V OL V in V IH V IL V M g g V M V OH V in V IH V IL linear approximation V out V M
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I D = I Dp + I Dn = 0 0 )) ( 1 ( 2 ) 1 ( 2 = - + - - - + + - - DD V out V p Dsatp V Tp V D V in V Dsatp V p K out V n Dsatn
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This note was uploaded on 02/19/2012 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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week6 - VDD CMOS inverter VDPMOS S G ID- D Vin VGS- Vout D...

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