week7 - Power consumption in CMOS inverters *Dynamic power...

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Power consumption in CMOS inverters *Dynamic power Assume zero rise and fall time 2 DD L VDD V C E = ½ energy stored in C L 2 2 DD L C V C E = ½ energy consumed in PMOS independent of R transistor but depends on size 2 2 DD L C V C E = consumed in PMOS independent of of R transistor but depends on size for each cycle E C =E VDD =C L V DD P dynamic = E f 0 1 =C L V DD 2 f 0 1 *in a logic CKT total load caps ,C L = C L P dynamic = C L V DD 2 f 0 1 but not all the gates activated together P dynamic = C L V DD 2 f 0 1 = C L V DD 2 f P 0 1 P : probability of activation = C eff f V DD 2 effective capacitance C eff = C L P 0 1 P 0 1 may be 10% never 100% To reduce P dyn : VDD power supply reduction CL reduction of gate caps use minimum size where possible P 0 1 reduction of switching activity V DD C L V DD C L V DD C L
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VDD/Transistor sizing for minimum power Optimum fan-out = f=4 How about effect of VDD and transistor sizing on power? Simple case :
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week7 - Power consumption in CMOS inverters *Dynamic power...

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