week8 - Combinational Logic NAND I1 1 0 1 1 0 1 1 1 0 I1 I2...

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Combinational Logic NAND NOR NAND and NOR gates are easy to realize in CMOS Complementary CMOS Logic *Two input NAND 2 1 I I O = I 1 I 2 O 0 1 I 1 I 2 O I 1 I 2 O I 1 I 2 O I 1 I 2 O Pull-up network Pull-down network V DD V out A B Pull-up Pull-down in1 in2 in1 in2 V DD out Pull-up network Pull-down network
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*Two input NOR 2 1 I I O + = How to realize a complex function? ) ( C B A D F + + = Pull-up network Pull-down network I 1 I 2 O 0 1 V DD out in1 in2 in1 in2 Pull-up network Pull-down network A B C D B C D B C D B C D Vout V DD
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Transfer Characteristic & depends on the data input patterns assume 2-in nand & M2 has higher Threshold voltage than M1 due to body effect This has to become higher than T DD V V + 2 for the gate to activate output Propagation delay of Complementary CMOS gate Propagation delay & depends on the data input pattern & delay = L C Rp 2 69 . 0 & delay = 0.69RpC L & delay = 0.69Rp(C L +C internal node ) A B V DD M2 M1 A out Internal node No body effect V out body effect & Higher V T A B B A=1 B=1 A
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For NAND gate to have same pull-down delay(t phl ) as min-sized inverter, NMOS devices must be twice as wide to get same R N and PMOS devices remain unchanged. Widening NMOS increase capacitance so NAND gate will be always slower than inverter. For NOR gate to be as fast as inverter PMOS devices 2X larger than inverter and NMOS devices remain unchanged. NOR gate & stacking PMOS slows down the performance & NOR gates is generally slower than NAND gates How to account for internal node Use Elmore delay model Assume a 4-input NAND gates t PHL = 0.69(R 1 C 1 +(R 1 +R 2 )C 2 + (R 1 +R 2 +R 3 3 +(R 1 +R 2 +R 3 +R 4 L ) assuming identical NMOS devices t PH L = 0.69R N (C 1 +2C 2 +3C 3 +4C L ) V DD M1 M2 M3 M4 R4 R3 R2 R1 CL C3 C2 C1
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& due to internal nodes & t PLH
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week8 - Combinational Logic NAND I1 1 0 1 1 0 1 1 1 0 I1 I2...

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