week9 - Ratioed Logic Static logic Ratioed logic Resistor...

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Ratioed Logic Static logic Ratioed logic Ratioed logic # of transistors in complementary logic = 2N transistor in Ratioed logic = N+1 Advantages of Ratioed logic - less # of transistors - less interconnects less complex layout Disadvantages of ratioed logic - Static power consumption when output = 0 - Level ) depends on the ratio of PMOS to NMOS sizing - slower in H L transistors A 150k 75k 37k Resistor V DD PDN
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4-in NAND 4-in NOR Different logic path positive feedback. No direct path V DD 0 static power = 0 Out 1 0 Still Ratioed logic since the transition is affected by sizing V OL = 0 V DD out PDN Complementary PDN out out out V DD A B A B V DD out out L H V DD time
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Pass transistor AND gate Complementary Pass transistor logic AB B B AB F = + = AB B A A A B B B A B A B A B A B A A A B B A B B B A F = + = + + + = + + + = + + = + = ) ( ) ( ) ( out V DD in x in out x A O/B B B F=AB B=V DD ,A=0 V DD A=V DD ,B=0 V DD A,B= 0 V DD Pass transistor
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This note was uploaded on 02/19/2012 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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week9 - Ratioed Logic Static logic Ratioed logic Resistor...

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