week10 - Dynamic CMOS design uses N+2 transistors bit no...

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Dynamic CMOS design uses N+2 transistors bit no static power Clk=0 out=V DD ± precharge state as PMOS=on. NMOS=off Clk=1 out f(A,B,C,D) ± evaluation state as PMOS=off. NMOS =on During Clk=1 if out : V DD 0 then inputs change out cannot be charged to V DD and we have to wait till next cycle. Example Dynamic logic is faster than complementary logic due to smaller # transistors logical effort is less 2-in NOR : g dyn = 2/3, g stat = 5/3 Disadvantages during eval. V out cannot change from 0 V DD low NML since V M – V tn higher switching activity also a 0 1 = P 0 not P 0 (1-P 0 ) as the output goes to 1 at each Clk cycles trsnsition probability for N-input gate ( uniform dist.) n N 2 0 1 0 = a A B V DD C Clk Clk out PDN A B Clk V DD Clk )Clk C AB ( Clk out + + = C
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Dynamic Circuit Dynamic NOR Problems with Dynamic Ckts 1. Charge leakage These pmos and nmos have leakage and work against each other. Pmos charges the capacitance with its leakage current and nmos discharges the capacitance. Clk A B Clk Clk Clk A pmos nmos A Clk Vout Precharge Leakage during evaluation period
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To solve the problem we can add current bleeder 2. Charge sharing Precharge C L is charged to V DD Evaluation if B=0, A 0 1 , then the charge on C L is shared with C a To solve the problem we can precharge the internal nodes To avoid ratio problem and avoid static power consumption Clk Clk A Clk Clk A A Bleeder pmos has to be weak Becomes ratioed logic Clk V DD Cb A B=0 Clk Ca 0 0 = = t x x V V C L Clk Clk Clk out
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3. Capacitive Coupling Dynamic logic high impedance output node coupling can be a problem
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week10 - Dynamic CMOS design uses N+2 transistors bit no...

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