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Unformatted text preview: Implementing Strategies for Digital ICs Semi custom Design Flow 1. design capture using hardware description language (HDL) such as VHDL, Verilog, System C 2. logic Synthesis, module described by HDL 3. Prelayout Simulation and verification ( performance analysis based on estimated parasitics ) 4. Floor Planning & is done based on estimated module sizes 5. Placement & precise position of the cells is decided 6. Routing & interconnects between blocks 7. Extraction & model of the chip based on layout ( device size, parasitics, caps and res ) 8. Post layout simulation and verification 9. tape out Dig. Implementation Semi Custom Custom Cell based Arrayl based Standard Cell Compiled Cell Macro Cell Pre Diffused ( Gate Arrays ) Pre Wired FPQA ’ s take advantage of some pre- designed modules ( shorten the design time) Block such as INV, AND/NAND, OR/NOR, XOR.XNOR, MVX, ADDER comparator, counter are hand designed (lay-out) Automatically cell placement and routing using standard cells Custom design of a...
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This note was uploaded on 02/19/2012 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.
- Spring '09